LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 548

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
23.6.3 Clock and Signal Polarity register
Table 457. Vertical Timing register (TIMV, address 0x4000 8004) bit description
The POL register controls various details of clock timing and signal polarity.
Bits
9:0
15:10
23:16
31:24
Symbol
LPP
VSW
VFP
VBP
All information provided in this document is subject to legal disclaimers.
Description
Lines per panel.
This is the number of active lines per screen. The LPP field specifies
the total number of lines or rows on the LCD panel being controlled.
LPP is a 10-bit value allowing between 1 and 1024 lines. Program
the register with the number of lines per LCD panel, minus 1. For
dual panel displays, program the register with the number of lines on
each of the upper and lower panels.
Vertical synchronization pulse width.
This is the number of horizontal synchronization lines. The 6-bit VSW
field specifies the pulse width of the vertical synchronization pulse.
Program the register with the number of lines required, minus one.
The number of horizontal synchronization lines must be small (for
example, program to zero) for passive STN LCDs. The higher the
value the worse the contrast on STN LCDs.
Vertical front porch.
This is the number of inactive lines at the end of a frame, before the
vertical synchronization period. The 8-bit VFP field specifies the
number of line clocks to insert at the end of each frame. When a
complete frame of pixels is transmitted to the LCD display, the value
in VFP is used to count the number of line clock periods to wait.
After the count has elapsed, the vertical synchronization signal,
LCDFP, is asserted in active mode, or extra line clocks are inserted
as specified by the VSW bit-field in passive mode. VFP generates
0–255 line clock cycles. Program to zero on passive displays for
improved contrast.
Vertical back porch.
This is the number of inactive lines at the start of a frame, after the
vertical synchronization period. The 8-bit VBP field specifies the
number of line clocks inserted at the beginning of each frame. The
VBP count starts immediately after the vertical synchronization signal
for the previous frame has been negated for active mode, or the extra
line clocks have been inserted as specified by the VSW bit field in
passive mode. After this has occurred, the count value in VBP sets
the number of line clock periods inserted before the next frame. VBP
generates 0–255 extra line clock cycles. Program to zero on passive
displays for improved contrast.
Rev. 00.13 — 20 July 2011
Chapter 23: LPC18xx LCD
UM10430
© NXP B.V. 2011. All rights reserved.
548 of 1164
Reset
value
0x0
0x0
0x0
0x0