LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 930

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
40.10 JTAG flash programming interface
<Document ID>
User manual
40.9.10 IAP Status Codes
40.9.9 Re-invoke ISP
Table 870. Re-invoke ISP
Table 871. IAP Status Codes Summary
Debug tools can write parts of the flash image to the RAM and then execute the IAP call
"Copy RAM to Flash" repeatedly with proper offset.
Command
Input
Return Code
Result
Description
Status
Code
0
1
2
3
4
5
6
7
8
9
10
11
Mnemonic
CMD_SUCCESS
INVALID_COMMAND
SRC_ADDR_ERROR
DST_ADDR_ERROR
SRC_ADDR_NOT_MAPPED
DST_ADDR_NOT_MAPPED
COUNT_ERROR
INVALID_SECTOR
SECTOR_NOT_BLANK
SECTOR_NOT_PREPARED_
FOR_WRITE_OPERATION
COMPARE_ERROR
BUSY
Compare
Command code: 57 (decimal)
None
None.
This command is used to invoke the boot loader in ISP mode. It maps boot
vectors, sets the clock to 96 MHz, configures UART0 pins U0_RX and U0_TX,
resets TIMER1 and resets the U0FDR (see
used when a valid user program is present in the internal flash memory and the
P2_7 pin is not accessible to force the ISP mode. The command does not disable
the PLL1 hence it is possible to invoke the boot loader when the part is running off
the PLL1. In this case, the ISP utility must pass the PLL1 output frequency after
the autobaud handshake.
Another option is to disable the PLL1 and select the IRC as the clock source
before making this IAP call. In this case,the frequency sent by ISP is ignored and
IRC and PLL1 are used to generate a 14.748 MHz clock.
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Chapter 40: LPC18xx flash programming interface
Description
Command is executed successfully.
Invalid command.
Source address is not on a word boundary.
Destination address is not on a correct boundary.
Source address is not mapped in the memory map.
Count value is taken in to consideration where
applicable.
Destination address is not mapped in the memory
map. Count value is taken in to consideration where
applicable.
Byte count is not multiple of 4 or is not a permitted
value.
Sector number is invalid.
Sector is not blank.
Command to prepare sector for write operation was
not executed.
Source and destination data is not same.
Flash programming hardware interface is busy.
Table
678). This command may be
UM10430
© NXP B.V. 2011. All rights reserved.
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