UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 102

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
(7) Port 5 function register (PF5)
Note The KRn pin and TIQ0m pin are alternate-function pins. When using the pin as the TIQ0m pin, disable
Caution
KR0/TIQ01
KR1/TIQ02
KR2/TIQ03
KR3/TIQ00
PFCE52
PFCE51
PFCE50
KRn pin key return detection, which is the alternate function. (Clear the KRM.KRMn bit to 0.) Also, when
using the pin as the KRn pin, disable TIQ0m pin edge detection, which is the alternate function (n = 0 to 3,
m = 0 to 3).
Pin Name
After reset: 00H
PF5
0
0
1
1
0
0
1
1
0
0
1
1
When an output pin is pulled up at EV
PF5n
0
1
0
KRM.KRM0 bit = 0
KRM.KRM1 bit = 0
KRM.KRM2 bit = 0
KRM.KRM3 bit = 0
PFC52
PFC51
PFC50
0
1
0
1
0
1
0
1
0
1
0
1
Normal output (CMOS output)
N-ch open-drain output
R/W
Use as TIQ0m Pin
0
Control of normal output or N-ch open-drain output (n = 0 to 5)
Setting prohibited
TIQ03 input/KR2
TOQ03 input
RTP02 output
Setting prohibited
TIQ02 input/KR1
TOQ02 output
RTP01 output
Setting prohibited
TIQ01 input/KR0
TOQ01 output
RTP00 output
Address: FFFFFC6AH
PF55
PF54
Note
Note
Note
Specification of P52 pin alternate function
Specification of P51 pin alternate function
Specification of P50 pin alternate function
input
input
input
TQ0IOC1. TQ0TIG2, TQ0IOC1. TQ0TIG3 bits = 0
TQ0IOC1.TQ0TIG4, TQ0IOC1.TQ0TIG5 bits = 0
TQ0IOC1.TQ0TIG6, TQ0IOC1.TQ0TIG7 bits = 0
TQ0IOC1.TQ0TIG0, TQ0IOC1.TQ0TIG1 bits = 0
TQ0IOC2.TQ0EES0, TQ0IOC2.TQ0EES1 bits = 0
TQ0IOC2.TQ0ETS0, TQ0IOC2.TQ0ETS1 bits = 0
DD
PF53
or higher, be sure to set the PF5n bit to 1.
PF52
Use as KRn Pin
CHAPTER 4 PORT FUNCTIONS
PF51
PF50
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