UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 343

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UPD70F3740GC-UEU-AX

Manufacturer Part Number
UPD70F3740GC-UEU-AX
Description
MCU 32BIT V850ES/JX3 100-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3r
Datasheet

Specifications of UPD70F3740GC-UEU-AX

Core Processor
RISC
Core Size
32-Bit
Speed
32MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
84
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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V850ES/JG3
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
(e) Generation timing of compare match interrupt request signal (INTTQ0CCk)
CCRk buffer register
INTTQ0CCk signal
The timing of generation of the INTTQ0CCk signal in the external trigger pulse output mode differs from the
timing of other INTTQ0CCk signals; the INTTQ0CCk signal is generated when the count value of the 16-bit
counter matches the value of the CCRk buffer register.
Remark
Usually, the INTTQ0CCk signal is generated in synchronization with the next count up after the count value of
the 16-bit counter matches the value of the CCRk buffer register.
In the external trigger pulse output mode, however, it is generated one clock earlier. This is because the timing
is changed to match the timing of changing the output signal of the TOQ0k pin.
TOQ0k pin output
16-bit counter
Count clock
k = 1 to 3
D
k
− 2
D
k
− 1
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
D
D
k
k
D
k
+ 1
D
k
+ 2
Page 327 of 870

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