UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 871

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
I
Function Details of Function
2
C bus
IICC0 to IICC2
registers
IICS0 to IICS2
registers
IICF0 to IICF2
registers
IICCL0 to IICCL2
registers
I
clock setting
method
Start condition
Status during
arbitration and
interrupt request
signal generation
timing
When
IICFn.STCENn bit
= 0
When
IICFn.STCENn bit
= 1
2
C0n transfer
Set the SPTn bit to 1 only in master mode. However, when the IICRSVn bit is 0,
the SPTn bit must be set to 1 and a stop condition generated before the first
stop condition is detected following the switch to the operation enabled status.
For details, see 17.15 Cautions.
When the TRCn bit = 1, the WRELn bit is set to 1 during the ninth clock and the
wait state is canceled, after which the TRCn bit is cleared to 0 and the SDA0n
line is set to high impedance.
Accessing the IICSn register is prohibited in the following statuses. For details,
see 3.4.8 (2) Accessing specific on-chip peripheral I/O registers.
• When the CPU operates with the subclock and the main clock oscillation is
• When the CPU operates with the internal oscillation clock
The TRCn bit is cleared to 0 and SDA0n line becomes high impedance when
the WRELn bit is set to 1 and the wait state is canceled to 0 at the ninth clock by
TRCn bit = 1.
Write the STCENn bit only when operation is stopped (IICEn bit = 0).
When the STCENn bit = 1, the bus released status (IICBSYn bit = 0) is
recognized regardless of the actual bus status immediately after the I
operation is enabled. Therefore, to issue the first start condition (STTn bit = 1), it
is necessary to confirm that the bus has been released, so as to not disturb
other communications.
Write the IICRSVn bit only when operation is stopped (IICEn bit = 0).
Be sure to clear bits 7 and 6 to “0”.
Since the selection clock is f
register, clear the OCKS0 register to 00H (I
Since the selection clock is f
register, clear the OCKS1 register to 00H (I
When the IICCn.IICEn bit of the V850ES/JG3 is set to 1 while communications
with other devices are in progress, the start condition may be detected
depending on the status of the communication line. Be sure to set the
IICCn.IICEn bit to 1 when the SCL0n and SDA0n lines are high level.
When the IICCn.WTIMn bit = 1, an INTIICn signal occurs at the falling edge of
the ninth clock. When the WTIMn bit = 0 and the extension code’s slave address
is received, an INTIICn signal occurs at the falling edge of the eighth clock (n =
0 to 2).
When there is a possibility that arbitration will occur, set the SPIEn bit to 1 for
master device operation (n = 0 to 2).
Immediately after the I
(IICFn.IICBSYn bit = 1) is recognized regardless of the actual bus status. To
execute master communication in the status where a stop condition has not
been detected, generate a stop condition and then release the bus before
starting the master communication.
Use the following sequence for generating a stop condition.
<1> Set the IICCLn register.
<2> Set the IICCn.IICEn bit.
<3> Set the IICCn.SPTn bit.
Immediately after I
bit = 0) is recognized regardless of the actual bus status. To generate the first
start condition (IICCn.STTn bit = 1), it is necessary to confirm that the bus has
been released, so as to not disturb other communications.
stopped
2
C0n operation is enabled, the bus released status (IICBSYn
2
C0n operation is enabled, the bus communication status
XX
XX
regardless of the value set to the OCKS0
regardless of the value set to the OCKS1
Cautions
2
2
C division clock stopped status).
C division clock stopped status).
APPENDIX E LIST OF CAUTIONS
2
Cn bus
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