UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 878

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
Interrupt/
exception
processing
function
Function
ISPR register
Restoration
from software
exception
processing
Illegal opcode
definition
Restoration
from exception
trap
Restoration from
debug trap
INTF0, INTR0
registers
INTF3, INTR3
registers
INTF9H,
INTR9H
registers
NFC register
NMI pin
Details of
Function
If an interrupt is acknowledged while the ISPR register is being read in the
interrupt enabled (EI) status, the value of the ISPR register after the bits of the
register have been set by acknowledging the interrupt may be read. To accurately
read the value of the ISPR register before an interrupt is acknowledged, read the
register while interrupts are disabled (DI).
When the EP and NP bits are changed by the LDSR instruction during the
software exception processing, in order to restore the PC and PSW correctly
during recovery by the RETI instruction, it is necessary to set the EP bit back to 1
and the NP bit back to 0 using the LDSR instruction immediately before the RETI
instruction.
Since it is possible to assign this instruction to an illegal opcode in the future, it is
recommended that it not be used.
DBPC and DBPSW can be accessed only during the interval between the
execution of an illegal opcode and the DBRET instruction.
DBPC and DBPSW can be accessed only during the interval between the
execution of the DBTRAP instruction and the DBRET instruction.
When the function is changed from the external interrupt function (alternate
function) to the port function, an edge may be detected. Therefore, clear the
INTF0n and INTR0n bits to 00, and then set the port mode.
Be sure to clear the INTF0n and INTR0n bits to 00 when these registers are not
used as the NMI or INTP0 to INTP3 pins.
When the function is changed from the external interrupt function (alternate
function) to the port function, an edge may be detected. Therefore, clear the
INTF31 and INTR31 bits to 00, and then set the port mode.
The INTP7 pin and RXDA0 pin are alternate-function pins. When using the pin as
the RXDA0 pin, disable edge detection for the INTP7 alternate-function pin (clear
the INTF3.INTF31 bit and the INRT3.INTR31 bit to 0). When using the pin as the
INTP7 pin, stop UARTA0 reception (clear the UA0CTL0.UA0RXE bit to 0).
Be sure to clear the INTF31 and INTR31 bits to 00 when these registers are not
used as INTP7 pin.
When the function is changed from the external interrupt function (alternate
function) to the port function, an edge may be detected. Therefore, clear the
INTF9n and INTR9n bits to 0, and then set the port mode.
Be sure to clear the INTF9n and INTR9n bits to 00 when these registers are not
used as INTP4 to INTP6 pins.
After the sampling clock has been changed, it takes 3 sampling clocks to initialize
the digital noise eliminator. Therefore, if an INTP3 valid edge is input within these
3 sampling clocks after the sampling clock has been changed, an interrupt
request signal may be generated.
Therefore, be careful about the following points when using the interrupt and DMA
functions.
• When using the interrupt function, after the 3 sampling clocks have elapsed,
• When using the DMA function (started by INTP3), enable DMA after 3 sampling
The NMI pin and P02 pin are an alternate-function pin, and function as a normal
port pin after being reset. To enable the NMI pin, validate the NMI pin with the
PMC0 register. The initial setting of the NMI pin is “No edge detected”. Select the
NMI pin valid edge using the INTF0 and INTR0 registers.
enable interrupts after the interrupt request flag (PIC3.PIF3 bit) has been
cleared.
clocks have elapsed.
Cautions
APPENDIX E LIST OF CAUTIONS
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