UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 658

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
19.2.2 Restore
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
(1) From NMI pin input
Caution When the EP and NP bits are changed by the LDSR instruction during non-maskable interrupt
Remark
Execution is restored from the NMI servicing by the RETI instruction.
When the RETI instruction is executed, the CPU performs the following processing, and transfers control to the
address of the restored PC.
<1> Loads the restored PC and PSW from FEPC and FEPSW, respectively, because the PSW.EP bit is 0 and the
<2> Transfers control back to the address of the restored PC and PSW.
The processing of the RETI instruction is shown below.
PSW.NP bit is 1.
servicing, in order to restore the PC and PSW correctly during recovery by the RETI
instruction, it is necessary to set the EP bit back to 0 and the NP bit back to 1 using the LDSR
instruction immediately before the RETI instruction.
The solid line shows the CPU processing flow.
1
Original processing restored
PC
PSW
RETI instruction
Figure 19-3. RETI Instruction Processing
PSW.EP
PSW.NP
CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION
0
0
EIPC
EIPSW
1
PC
PSW
FEPC
FEPSW
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