UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 881

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
Reset
function
Clock
monitor
Low-
voltage
detector
(LVI)
CRC
function
Regulator Regulator
Flash
memory
Function
Hardware status
on RESET pin
input
CLM register
Internal
oscillator
LVIM register
LVIS register
To use for
internal reset
signal
To use for
interrupt
PEMU1 register This bit is not automatically cleared.
CRCD register
FLMD1 pin
PG-FP4
FA-144GJ-UEN-A
Details of
Function
•
•
The OCDM register is initialized by the RESET pin input. Therefore, note with
caution that, if a high level is input to the P05/DRST pin after a reset release
before the OCDM.OCDM0 bit is cleared, the on-chip debug mode is entered. For
details, see CHAPTER 4 PORT FUNCTIONS.
Once the CLME bit has been set to 1, it cannot be cleared to 0 by any means
other than reset.
When a reset by the clock monitor occurs, the CLME bit is cleared to 0 and the
RESF.CLMRF bit is set to 1.
The internal oscillator can be stopped by setting the RCM.RSTOP bit to 1.
The clock monitor is stopped while the internal oscillator is stopped.
The internal oscillator cannot be stopped by software.
When the LVION and LVIMD bits to 1, the low-voltage detector cannot be
stopped until the reset request due to other than the low-voltage detection is
generated.
When the LVION bit is set to 1, the comparator in the LVI circuit starts operating.
Wait 0.2 ms or longer by software before checking the voltage at the LVIF bit after
the LVION bit is set.
Be sure to clear bits 6 to 2 to “0”.
This register cannot be written until a reset request due to something other than
low-voltage detection is generated after the LVIM.LVION and LVIM.LVIMD bits
are set to 1.
Be sure to clear bits 7 to 1 to “0”.
If the LVIMD bit is set to 1, the contents of the LVIM and LVIS registers cannot be
changed until a reset request other than LVI is generated.
When the INTLVI signal is generated, confirm, using the LVIM/LVIF bit, whether
the INTLVI signal is generated due to a supply voltage drop or rise across the
detected voltage.
Accessing the CRCD register is prohibited in the following statuses. For details,
refer to 3.4.9 (2) Accessing specific on-chip peripheral I/O registers.
Use the regulator with a setting of V
Connect the FLMD1 pin to the flash programmer or connect to a GND via a pull-
down resistor on the board.
Wire these pins as shown in Figure 27-6, or connect then to GND via pull-down
resistor on board.
Clock cannot be supplied via the CLK pin of the flash programmer. Create an
oscillator on board and supply the clock.
Be sure to connect the REGC pin to GND via a 4.7
capacitor.
A clock cannot be supplied from the CLK pin of the flash programmer. Create an
oscillator on the board and supply the clock from that oscillator.
When the CPU operates with the subclock and the main clock oscillation is
stopped
When the CPU operates with the internal oscillation clock
DD
Cautions
= EV
DD
= AV
APPENDIX E LIST OF CAUTIONS
REF0
μ
F (recommended value)
= AV
REF1
.
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