UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 593

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
17.7.4 Operation without communication
17.7.5 Arbitration loss operation (operation as slave after arbitration loss)
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
(1) Start ~ Code ~ Data ~ Data ~ Stop
(1) When arbitration loss occurs during transmission of slave address data
<1> When IICCn.WTIMn bit = 0
<2> When WTIMn bit = 1
ST
ST
ST
Δ 1: IICSn register = 00000001B
Δ 4: IICSn register = 00000001B
Δ 4: IICSn register = 00000001B
Remarks 1. Δ: Generated only when SPIEn bit = 1
Remarks 1.
Remarks 1.
1: IICSn register = 0101X110B (Example: When IICSn.ALDn bit is read during interrupt servicing)
2: IICSn register = 0001X000B
3: IICSn register = 0001X000B
1: IICSn register = 0101X110B (Example: When ALDn bit is read during interrupt servicing)
2: IICSn register = 0001X100B
3: IICSn register = 0001XX00B
AD6 to AD0
AD6 to AD0
AD6 to AD0
2. n = 0 to 2
2. n = 0 to 2
2. n = 0 to 2
Δ: Generated only when IICCn.SPIEn bit = 1
X: don’t care
Δ: Generated only when SPIEn bit = 1
X: don’t care
: Always generated
: Always generated
R/W
R/W
R/W
ACK
ACK
ACK
1
1
D7 to D0
D7 to D0
D7 to D0
2
ACK
ACK
ACK
2
D7 to D0
D7 to D0
D7 to D0
3
ACK
ACK
ACK
3
SP
SP
SP
Δ1
Δ4
Δ4
CHAPTER 17 I
Page 577 of 870
2
C BUS