UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 876

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
DMA
function
(DMA
controller)
Function
DMA transfer
initialization
procedure
(setting
DCHCn.INITn
bit to 1)
Procedure of
temporarily
stopping DMA
transfer
(clearing Enn
bit)
Memory
boundary
Transferring
misaligned data
Bus arbitration
for CPU
Registers/bits
that must not be
rewritten during
DMA operation
DSAnH register
DDAnH register
DADCn register
DCHCn register
Details of
Function
Stop and resume the DMA transfer under execution using the following
procedure.
<1> Suppress a transfer request from the DMA request source (stop the operation
<2> Check the DMA transfer request is not held pending, by using the DFn bit
<3> If it has been confirmed that no DMA transfer request is held pending, clear
<4> Set the Enn bit to 1 to resume DMA transfer.
<5> Resume the operation of the DMA request source that has been stopped
The operation is not guaranteed if the address of the transfer source or
destination exceeds the area of the DMA target (external memory, internal RAM,
or on-chip peripheral I/O) during DMA transfer.
DMA transfer of misaligned data with a 16-bit bus width is not supported.
If an odd address is specified as the transfer source or destination, the least
significant bit of the address is forcibly assumed to be 0.
Because the DMA controller has a higher priority bus mastership than the CPU, a
CPU access that takes place during DMA transfer is held pending until the DMA
transfer cycle is completed and the bus is released to the CPU.
However, the CPU can access the external memory, on-chip peripheral I/O, and
internal RAM to/from which DMA transfer is not being executed.
• The CPU can access the internal RAM when DMA transfer is being executed
• The CPU can access the internal RAM and on-chip peripheral I/O when DMA
Set the following registers at the following timing when a DMA operation is not
under execution.
[Registers]
• DSAnH, DSAnL, DDAnH, DDAnL, DBCn, and DADCn registers
• DTFRn.IFCn5 to DTFRn.IFCn0 bits
[Timing of setting]
• Period from after reset to start of the first DMA transfer
• Time after channel initialization to start of DMA transfer
• Period from after completion of DMA transfer (TCn bit = 1) to start of the next
DMA transfer
Be sure to set the following register bits to 0.
• Bits 14 to 10 of DSAnH register
• Bits 14 to 10 of DDAnH register
• Bits 15, 13 to 8, and 3 to 0 of DADCn register
• Bits 6 to 3 of DCHCn register
between the external memory and on-chip peripheral I/O.
transfer is being executed between the external memory and external memory.
<4> Again, clear the Enn bit of the channel to be forcibly terminated.
<5> Copy the initial number of transfers of the channel to be forcibly
<6> Set the INITn bit of the channel to be forcibly terminated to 1.
<7> Read the value of the DBCn register of the channel to be forcibly
of the on-chip peripheral I/O).
(check if the DFn bit = 0).
If a request is pending, wait until execution of the pending DMA transfer
request is completed.
the Enn bit to 0 (this operation stops DMA transfer).
(start the operation of the onchip peripheral I/O).
If the target of transfer for the channel to be forcibly terminated (transfer
source/destination) is the internal RAM, execute this operation once
more.
terminated to a general-purpose register.
terminated, and compare it with the value copied in <5>. If the two values
do not match, repeat operations <6> and <7>.
Cautions
APPENDIX E LIST OF CAUTIONS
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