UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 685

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
19.7 Interrupt Acknowledge Time of CPU
signals successively, input the next interrupt request signal at least 5 clocks after the preceding interrupt.
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
Except the following cases, the interrupt acknowledge time of the CPU is 4 clocks minimum. To input interrupt request
• In IDLE1/IDLE2/STOP mode
• When the external bus is accessed
• When interrupt request non-sampling instructions are successively executed (see 19.8 Periods in Which Interrupts
• When the interrupt control register is accessed
(1) Minimum interrupt response time
(2) Maximum interrupt response time
Remark
Are Not Acknowledged by CPU.)
Minimum
Maximum
Instruction (first instruction of interrupt servicing routine)
Interrupt acknowledge time (internal system clock)
Instruction (first instruction of interrupt servicing routine)
INT1 to INT4: Interrupt acknowledgment processing
IFX:
IDX:
Figure 19-15. Pipeline Operation at Interrupt Request Signal Acknowledgment (Outline)
Internal interrupt
Interrupt acknowledgment operation
Interrupt acknowledgment operation
4
6
Invalid instruction fetch
Invalid instruction decode
Analog delay time
Analog delay time
External interrupt
Interrupt request
CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION
Interrupt request
Internal clock
4 +
6 +
Instruction 1
Instruction 2
Internal clock
Instruction 1
Instruction 2
The following cases are exceptions.
• In IDLE1/IDLE2/STOP mode
• External bus access
• Two or more interrupt request non-sample instructions are
• Access to peripheral I/O register
executed in succession
IF
IF
INT1 INT2 INT3 INT3 INT3 INT4
IFX IDX
ID
INT1 INT2 INT3 INT4
IFX IDX
ID
4 system clocks
EX MEM MEM MEM WB
EX MEM WB
6 system clocks
Condition
IF
ID
IF
EX
ID
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