UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 848

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
SUB
SUBR
SWITCH
SXB
SXH
TRAP
TST
TST1
XOR
XORI
ZXB
ZXH
Mnemonic
Notes 1.
reg1,reg2
reg1,reg2
reg1
reg1
reg1
vector
reg1,reg2
bit#3,disp16[reg1]
reg2, [reg1]
reg1,reg2
imm16,reg1,reg2
reg1
reg1
2.
3.
4.
5.
6.
7.
8.
9.
10. b: bit 0 of disp16.
11. According to the number of wait states (2 if there are no wait states).
Operand
According to the number of wait states (1 if there are no wait states).
dddddddd: Higher 8 bits of disp9.
3 if there is an instruction that rewrites the contents of the PSW immediately before.
If there is no wait state (3 + the number of read access wait states).
n is the total number of list12 load registers. (According to the number of wait states. Also, if there are no
wait states, n is the total number of list12 registers. If n = 0, same operation as when n = 1)
RRRRR: other than 00000.
The lower halfword data only are valid.
ddddddddddddddddddddd: The higher 21 bits of disp22.
ddddddddddddddd: The higher 15 bits of disp16.
r r rr r0 01 10 1 RRRRR GR[reg2]←GR[reg2]–GR[reg1]
r r rr r0 01 10 0 RRRRR GR[reg2]←GR[reg1]–GR[reg2]
00000000010RRRRR adr←(PC+2) + (GR [reg1] logically shift left by 1)
00000000101RRRRR GR[reg1]←sign-extend
00000000111RRRRR GR[reg1]←sign-extend
0 0 0 0 0 1 1 1 1 1 1 i i i i i
0000000100000000
r r rr r0 01 01 1 RRRRR result←GR[reg2] AND GR[reg1]
11bbb111110RRRRR
dddddddddddddddd
r r rr r1 11 11 1 RRRRR
0000000011100110
r r rr r0 01 00 1 RRRRR GR[reg2]←GR[reg2] XOR GR[reg1]
r r rr r1 10 10 1 RRRRR
i i i i i i i i i i i i i i i i
00000000100RRRRR GR[reg1]←zero-extend (GR[reg1] (7 : 0))
00000000110RRRRR GR[reg1]←zero-extend (GR[reg1] (15 : 0))
Opcode
PC←(PC+2) + (sign-extend
(Load-memory (adr,Halfword))
logically shift left by 1
(GR[reg1] (7 : 0))
(GR[reg1] (15 : 0))
EIPC
EIPSW
ECR.EICC ←Interrupt code
PSW.EP
PSW.ID
PC
adr←GR[reg1]+sign-extend(disp16)
Z flag←Not (Load-memory-bit (adr,bit#3))
adr←GR[reg1]
Z flag←Not (Load-memory-bit (adr,reg2))
GR[reg2]←GR[reg1] XOR zero-extend (imm16)
←PC+4 (Restored PC)
←PSW
←1
←1
←00000040H
(when vector is 00H to 0FH)
00000050H
(when vector is 10H to 1FH)
Operation
APPENDIX D INSTRUCTION SET LIST
Note 3
Note 3
1
1
5
1
1
3
3
3
1
1
1
1
1
Execution
i
Clock
Note 3
Note 3
1
1
5
1
1
3
1
3
3
1
1
1
1
r
Note 3
Note 3
1
1
5
1
1
3
1
3
3
1
1
1
1
l
CY OV S
×
×
×
×
0
0
0
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Flags
×
×
×
×
×
Z SAT
×
×
×
×
×
×
×
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