UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 506

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
Notes 1. If the CBnSCE bit is read while it is 1, the next communication operation is started.
Caution Be sure to clear bits 3 and 2 to “0”.
CBnSCE
• In master mode
• In slave mode
[Usage of CBnSCE bit]
• In single reception mode
• In continuous reception mode
This bit enables or disables the communication start trigger.
(a) In single transmission or transmission/reception mode, or continuous
(b) In single reception mode
(c) In continuous reception mode
This bit enables or disables the communication start trigger.
Set the CBnSCE bit to 1.
<1>When reception of the last data is completed by INTCBnR interrupt
<2>After confirming the CBnSTR.CBnTSF bit = 0, clear the CBnRXE bit to 0 to
<1>Clear the CBnSCE bit to 0 during the reception of the last data by INTCBnR
<2>Read the CBnRX register.
<3>Read the last reception data by reading the CBnRX register after
<4>After confirming the CBnSTR.CBnTSF bit = 0, clear the CBnRXE bit to 0 to
0
1
2. The CBnSCE bit is not cleared to 0 one communication clock before the completion of
transmission or continuous transmission/reception mode
The setting of the CBnSCE bit has no influence on communication operation.
Clear the CBnSCE bit to 0 before reading the last receive data because
reception is started by reading the receive data (CBnRX register) to disable
the reception startup
Clear the CBnSCE bit to 0 one communication clock before reception of the
last data is completed to disable the reception startup after the last data is
received
servicing, clear the CBnSCE bit to 0 before reading the CBnRX register.
disable reception.
To continue reception, set the CBnSCE bit to 1 to start up the next reception
by dummy-reading the CBnRX register.
interrupt servicing.
acknowledging the CBnTIR interrupt.
disable reception.
To continue reception, set the CBnSCE bit to 1 to wait for the next reception
by dummy-reading the CBnRX register.
the last data reception, the next communication operation is automatically started.
Communication start trigger invalid
Communication start trigger valid
Note 2
.
Specification of start transfer disable/enable
CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB)
Note 1
.
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