UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 537

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
SIBn pin capture
INTCBnR signal
(2) Operation timing
CBnSCE bit
CBnTSF bit
SCKBn pin
(1) Write 07H to the CBnCTL1 register, and select communication type 1, communication clock (f
(2) Write 00H to the CBnCTL2 register, and set the transfer data length to 8 bits.
(3) Write A3H to the CBnCTL0 register, and select the reception mode, MSB first, and continuous transfer
(4) The CBnSTR.CBnTSF bit is set to 1 by performing a dummy read of the CBnRX register, and the
(5) When a serial clock is input, capture the receive data of the SIBn pin in synchronization with the serial
(6) When reception is completed, the reception completion interrupt request signal (INTCBnR) is
(7) When a serial clock is input in the CBnCTL0.CBnSCE bit = 1 status, continuous reception is started.
(8) To end continuous reception with the current reception, write the CBnSCE bit = 0.
(9) Read the CBnRX register.
(10) When reception is completed, the INTCBnR signal is generated, and reading of the CBnRX register is
(11) Read the CBnRX register.
(12) If an overrun error occurs, write the CBnSTR.CBnOVE bit = 0, and clear the error flag.
(13) To release the reception enable status, write the CBnCTL0.CBnPWR bit = 0 and the
Remark
SIBn pin
timing
external clock (SCKBn), and slave mode.
mode at the same time as enabling the operation of the communication clock (f
device waits for a serial clock input.
clock.
generated, and reading of the CBnRX register is enabled.
enabled. When the CBnSCE bit = 0 is set before communication completion, clear the CBnTSF bit to
0 to end the receive operation.
CBnCTL0.CBnRXE bit = 0 after checking that the CBnTSF bit = 0.
(1)
(2)
(3)
n = 0 to 4
(4)
(5)
Bit 7
Bit 6
Bit 5
Bit 4 Bit 3
CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB)
Bit 2
Bit 1
(6) (7) (8) (9)
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4 Bit 3
Bit 2
Bit 1
(10)
Bit 0
CCLK
).
(11) (13)
Page 521 of 870
CCLK
) =