UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 68

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
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Address
Data wait control register 0
Address wait control register
Bus cycle control register
TMQ0 control register 0
TMQ0 control register 1
TMQ0 I/O control register 0
TMQ0 I/O control register 1
TMQ0 I/O control register 2
TMQ0 option register 0
TMQ0 capture/compare register 0
TMQ0 capture/compare register 1
TMQ0 capture/compare register 2
TMQ0 capture/compare register 3
TMQ0 counter read buffer register
TMP0 control register 0
TMP0 control register 1
TMP0 I/O control register 0
TMP0 I/O control register 1
TMP0 I/O control register 2
TMP0 option register 0
TMP0 capture/compare register 0
TMP0 capture/compare register 1
TMP0 counter read buffer register
TMP1 control register 0
TMP1 control register 1
TMP1 I/O control register 0
TMP1 I/O control register 1
TMP1 I/O control register 2
TMP1 option register 0
TMP1 capture/compare register 0
TMP1 capture/compare register 1
TMP1 counter read buffer register
TMP2 control register 0
TMP2 control register 1
TMP2 I/O control register 0
TMP2 I/O control register 1
TMP2 I/O control register 2
TMP2 option register 0
TMP2 capture/compare register 0
TMP2 capture/compare register 1
TMP2 counter read buffer register
TMP3 control register 0
TMP3 control register 1
Function Register Name
DWC0
AWC
BCC
TQ0CTL0
TQ0CTL1
TQ0IOC0
TQ0IOC1
TQ0IOC2
TQ0OPT0
TQ0CCR0
TQ0CCR1
TQ0CCR2
TQ0CCR3
TQ0CNT
TP0CTL0
TP0CTL1
TP0IOC0
TP0IOC1
TP0IOC2
TP0OPT0
TP0CCR0
TP0CCR1
TP0CNT
TP1CTL0
TP1CTL1
TP1IOC0
TP1IOC1
TP1IOC2
TP1OPT0
TP1CCR0
TP1CCR1
TP1CNT
TP2CTL0
TP2CTL1
TP2IOC0
TP2IOC1
TP2IOC2
TP2OPT0
TP2CCR0
TP2CCR1
TP2CNT
TP3CTL0
TP3CTL1
Symbol
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
CHAPTER 3 CPU FUNCTION
Manipulatable Bits
1
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
8
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
16
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
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00H
00H
00H
00H
00H
00H
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0000H
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0000H
00H
00H
00H
00H
00H
00H
0000H
0000H
0000H
00H
00H
00H
00H
00H
00H
0000H
0000H
0000H
00H
00H
00H
00H
00H
00H
0000H
0000H
0000H
00H
00H
Default Value
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