UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 722

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
(3) Operation in STOP mode or after STOP mode is released
(4) Operation when main clock is stopped (arbitrary)
(5) Operation while CPU is operating on internal oscillation clock (CCLS.CCLSF bit = 1)
Internal oscillation
Internal oscillation
If the STOP mode is set with the CLM.CLME bit = 1, the monitor operation is stopped in the STOP mode and while
the oscillation stabilization time is being counted. After the oscillation stabilization time, the monitor operation is
automatically started.
During subclock operation (PCC.CLS bit = 1) or when the main clock is stopped by setting the PCC.MCK bit to 1,
the monitor operation is stopped until the main clock operation is started (PCC.CLS bit = 0). The monitor operation
is automatically started when the main clock operation is started.
The monitor operation is not stopped when the CCLSF bit is 1, even if the CLME bit is set to 1.
Clock monitor
Clock monitor
Main clock
Main clock
operation
operation
CLME
CLME
status
status
clock
clock
CPU
CPU
operation
Figure 23-4. Operation in STOP Mode or After STOP Mode Is Released
Normal
monitor
monitor
During
During
Figure 23-5. Operation When Main Clock Is Stopped (Arbitrary)
PCC.MCK bit = 1
Oscillation stops
Oscillation stops
Monitor stops
STOP
Subclock operation
Oscillation stabilization time
Monitor stops
Oscillation stabilization time
Oscillation stabilization time
Oscillation stabilization
time count by software
(set by OSTS register)
(set by OSTS register)
Monitor stops
CHAPTER 23 CLOCK MONITOR
Main clock operation
Normal operation
During monitor
During monitor
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