UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 875

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
DMA
function
(DMA
controller)
Function
Caution for
DMA transfer
executed on
internal RAM
Caution for
reading
DCHCn.TCn bit
DMA transfer
initialization
procedure
(setting
DCHCn.INITn
bit to 1)
Details of
Function
When executing the following instructions located in the internal RAM, do not
execute a DMA transfer that transfers data to/from the internal RAM (transfer
source/destination), because the CPU may not operate correctly afterward.
• Bit manipulation instruction located in internal RAM (SET1, CLR1, or NOT1)
• Data access instruction to misaligned address located in internal RAM
Conversely, when executing a DMA transfer to transfer data to/from the internal
RAM (transfer source/destination), do not execute the above two instructions.
The TCn bit is cleared to 0 when it is read, but it is not automatically cleared even
if it is read at a specific timing. To accurately clear the TCn bit, add the following
processing.
(a) When waiting for completion of DMA transfer by polling TCn bit
(b) When reading TCn bit in interrupt servicing routine
Even if the INITn bit is set to 1 when the channel executing DMA transfer is to be
initialized, the channel may not be initialized. To accurately initialize the channel,
execute either of the following two procedures.
(a) Temporarily stop transfer of all DMA channels
Be sure to execute step <5> above to prevent illegal setting of the Enn bit of the
channels whose DMA transfer has been normally completed between <2> and
<3>.
(b) Repeatedly execute setting INITn bit until transfer is forcibly terminated
Confirm that the TCn bit has been set to 1 (after TCn bit = 1 is read), and then
read the TCn bit three more times.
Execute reading the TCn bit three times.
Initialize the channel executing DMA transfer using the procedure in <1> to
<7> below.
Note, however, that TCn bit is cleared to 0 when step <5> is executed. Make
sure that the other processing programs do not expect that the TCn bit is 1.
<1> Disable interrupts (DI).
<2> Read the DCHCn.Enn bit of DMA channels other than the one to be
<3> Clear the Enn bit of the DMA channels used (including the channel to be
<4> Set the INITn bit of the channel to be forcibly terminated to 1.
<5> Read the TCn bit of each channel not to be forcibly terminated. If both the
<6> After the operation in <5>, write the Enn bit value to the DCHCn register.
<7> Enable interrupts (EI).
correctly
<1> Suppress a request from the DMA request source of the channel to be
<2> Check that the DMA transfer request of the channel to be forcibly
<3> When it has been confirmed that the DMA request of the channel to be
forcibly terminated, and transfer the value to a general-purpose register.
forcibly terminated) to 0. To clear the Enn bit of the last DMA channel,
execute the clear instruction twice. If the target of DMA transfer (transfer
source/destination) is the internal RAM, execute the instruction three
times.
TCn bit and the Enn bit read in <2> are 1 (logical product (AND) is 1),
clear the saved Enn bit to 0.
forcibly terminated (stop operation of the on-chip peripheral I/O).
terminated is not held pending, by using the DTFRn.DFn bit. If a DMA
transfer request is held pending, wait until execution of the pending
request is completed.
forcibly terminated is not held pending, clear the Enn bit to 0.
Example: Execute instructions in the following order if channels 0, 1, and
2 are used (if the target of transfer is not the internal RAM).
• Clear DCHC0.E00 bit to 0.
• Clear DCHC1.E11 bit to 0.
• Clear DCHC2.E22 bit to 0.
• Clear DCHC2.E22 bit to 0 again.
Cautions
APPENDIX E LIST OF CAUTIONS
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