UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 847

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
SET1
SHL
SHR
SLD.B
SLD.BU
SLD.H
SLD.HU
SLD.W
SST.B
SST.H
SST.W
ST.B
ST.H
ST.W
STSR
Mnemonic
bit#3,disp16[reg1]
reg2,[reg1]
reg1,reg2
imm5,reg2
reg1,reg2
imm5,reg2
disp7[ep],reg2
disp4[ep],reg2
disp8[ep],reg2
disp5[ep],reg2
disp8[ep],reg2
reg2,disp7[ep]
reg2,disp8[ep]
reg2,disp8[ep]
reg2,disp16[reg1]
reg2,disp16[reg1]
reg2,disp16[reg1]
regID,reg2
Operand
00bbb111110RRRRR
dddddddddddddddd
r r rr r1 11 11 1 RRRRR
0000000011100000
r r rr r1 11 11 1 RRRRR
0000000011000000
r r r r r 0 1 0 1 1 0 i i i i i
r r rr r1 11 11 1 RRRRR
0000000010000000
r r r r r 0 1 0 1 0 0 i i i i i
r r r r r 0 1 1 0 d d d d d d d
r r r r r 0 1 1 1 d d d d d d d
r r rr r1 11 01 0 RRRRR
dddddddddddddddd
r r rr r1 11 11 1 RRRRR
0000000001000000
r r r r r 0 0 0 0 1 1 1 d d d d
r r r r r 1 0 1 0 d d d d d d 0
r r r r r 1 0 1 0 d d d d d d 1
r r rr r1 11 01 1 RRRRR
r r r r r 0 0 0 0 1 1 0 d d d d
r r r r r 1 0 0 0 d d d d d d d
r r r r r 1 0 0 1 d d d d d d d
ddddddddddddddd0
ddddddddddddddd1
rrrrr111011RRRRR
Opcode
Notes 18, 20
Note 18
Note 19
Note 21
Note 19
Note 21
Note 8
Note 8
adr←GR[reg1]+sign-extend(disp16)
Z flag←Not (Load-memory-bit(adr,bit#3))
Store-memory-bit(adr,bit#3,1)
adr←GR[reg1]
Z flag←Not(Load-memory-bit(adr,reg2))
Store-memory-bit(adr,reg2,1)
GR[reg2]←GR[reg2] logically shift left by GR[reg1]
GR[reg2]←GR[reg2] logically shift left
by zero-extend(imm5)
GR[reg2]←GR[reg2] logically shift right by GR[reg1]
GR[reg2]←GR[reg2] logically shift right
by zero-extend(imm5)
adr←ep+zero-extend(disp7)
GR[reg2]←sign-extend(Load-memory(adr,Byte))
adr←ep+zero-extend(disp4)
GR[reg2]←zero-extend(Load-memory(adr,Byte))
adr←ep+zero-extend(disp8)
GR[reg2]←sign-extend(Load-memory(adr,Halfword))
adr←ep+zero-extend(disp5)
GR[reg2]←zero-extend(Load-memory(adr,Halfword))
adr←ep+zero-extend(disp8)
GR[reg2]←Load-memory(adr,Word)
adr←ep+zero-extend(disp7)
Store-memory(adr,GR[reg2],Byte)
adr←ep+zero-extend(disp8)
Store-memory(adr,GR[reg2],Halfword)
adr←ep+zero-extend(disp8)
Store-memory(adr,GR[reg2],Word)
adr←GR[reg1]+sign-extend(disp16)
Store-memory(adr,GR[reg2],Byte)
adr←GR[reg1]+sign-extend(disp16)
Store-memory (adr,GR[reg2], Halfword)
adr←GR[reg1]+sign-extend(disp16)
Store-memory (adr,GR[reg2], Word)
GR[reg2]←SR[regID]
Operation
APPENDIX D INSTRUCTION SET LIST
Note 3
Note 3
3
3
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Execution
i
Clock
Note 3
Note 3
3
3
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
r
Note 3
Note 3
Note 9
Note 9
Note 9
Note 9
Note 9
3
3
1
1
1
1
1
1
1
1
1
1
1
l
CY OV S
×
×
×
×
0
0
0
0
Page 831 of 870
Flags
×
×
×
×
Z SAT
×
×
×
×
×
×
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