UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 686

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
19.8 Periods in Which Interrupts Are Not Acknowledged by CPU
acknowledged between an interrupt request non-sample instruction and the next instruction (interrupt is held pending).
19.9 Cautions
the NMI pin, validate the NMI pin with the PMC0 register. The initial setting of the NMI pin is “No edge detected”. Select
the NMI pin valid edge using the INTF0 and INTR0 registers.
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
An interrupt is acknowledged by the CPU while an instruction is being executed. However, no interrupt will be
The interrupt request non-sample instructions are as follows.
• EI instruction
• DI instruction
• LDSR reg2, 0x5 instruction (for PSW)
• The store instruction for the PRCMD register
• The store, SET1, NOT1, or CLR1 instructions for the following registers.
The NMI pin and P02 pin are an alternate-function pin, and function as a normal port pin after being reset. To enable
Remark xx: Identification name of each peripheral unit (see Table 19-2 Interrupt Control Register (xxICn))
• Interrupt-related registers:
• Power save control register (PSC)
• On-chip debug mode register (OCDM)
Interrupt control register (xxICn), interrupt mask registers 0 to 3 (IMR0 to IMR3)
n: Peripheral unit number (see Table 19-2 Interrupt Control Register (xxICn)).
CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION
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