UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 14

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

CHAPTER 20 KEY INTERRUPT FUNCTION ..................................................................................... 671
CHAPTER 21 STANDBY FUNCTION .................................................................................................. 673
CHAPTER 22 RESET FUNCTIONS ..................................................................................................... 693
19.5
19.6
19.7
19.8
19.9
20.1
20.2
20.3
21.1
21.2
21.3
21.4
21.5
21.6
21.7
21.8
22.1
22.2
22.3
19.4.1
19.4.2
19.4.3
Exception Trap...................................................................................................................... 660
19.5.1
19.5.2
External Interrupt Request Input Pins (NMI and INTP0 to INTP7) ................................... 664
19.6.1
19.6.2
Interrupt Acknowledge Time of CPU .................................................................................. 669
Periods in Which Interrupts Are Not Acknowledged by CPU .......................................... 670
Cautions ................................................................................................................................ 670
Function................................................................................................................................. 671
Register ................................................................................................................................. 672
Cautions ................................................................................................................................ 672
Overview................................................................................................................................ 673
Registers ............................................................................................................................... 675
HALT Mode............................................................................................................................ 678
21.3.1
21.3.2
IDLE1 Mode ........................................................................................................................... 680
21.4.1
21.4.2
IDLE2 Mode ........................................................................................................................... 682
21.5.1
21.5.2
21.5.3
STOP Mode............................................................................................................................ 685
21.6.1
21.6.2
21.6.3
Subclock Operation Mode ................................................................................................... 689
21.7.1
21.7.2
Sub-IDLE Mode ..................................................................................................................... 691
21.8.1
21.8.2
Overview................................................................................................................................ 693
Registers to Check Reset Source....................................................................................... 694
Operation............................................................................................................................... 695
22.3.1
22.3.2
22.3.3
22.3.4
Operation .................................................................................................................................657
Restore ....................................................................................................................................658
EP flag .....................................................................................................................................659
Illegal opcode definition............................................................................................................660
Debug trap ...............................................................................................................................662
Noise elimination......................................................................................................................664
Edge detection .........................................................................................................................664
Setting and operation status ....................................................................................................678
Releasing HALT mode.............................................................................................................678
Setting and operation status ....................................................................................................680
Releasing IDLE1 mode ............................................................................................................680
Setting and operation status ....................................................................................................682
Releasing IDLE2 mode ............................................................................................................682
Securing setup time when releasing IDLE2 mode ...................................................................684
Setting and operation status ....................................................................................................685
Releasing STOP mode ............................................................................................................685
Securing oscillation stabilization time when releasing STOP mode .........................................688
Setting and operation status ....................................................................................................689
Releasing subclock operation mode ........................................................................................689
Setting and operation status ....................................................................................................691
Releasing sub-IDLE mode .......................................................................................................691
Reset operation via RESET pin ...............................................................................................695
Reset operation by watchdog timer 2.......................................................................................697
Reset operation by low-voltage detector ..................................................................................699
Operation after reset release ...................................................................................................700