UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 413

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
WDCS24
(2) Watchdog timer enable register (WDTE)
Cautions 1. When a value other than “ACH” is written to the WDTE register, an overflow signal is
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
The counter of watchdog timer 2 is cleared and counting restarted by writing “ACH” to the WDTE register.
The WDTE register can be read or written in 8-bit units.
Reset sets this register to 9AH.
WDCS23
2. When a 1-bit memory manipulation instruction is executed for the WDTE register, an
3. To intentionally generate an overflow signal, write a value other than “ACH” to the WDTE
4. The read value of the WDTE register is “9AH” (which differs from written value “ACH”).
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
×
×
×
×
×
×
×
×
WDTE
After reset: 9AH
forcibly output.
overflow signal is forcibly output.
register only once, or write data to the WDTM2 register only twice.
However, when the watchdog timer 2 is set to stop operation, an overflow signal is not
generated even if data is written to the WDTM2 register only twice, or a value other than
“ACH” is written to the WDTE register only once.
WDCS22
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
WDCS21
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
R/W
Table 11-2. Watchdog Timer 2 Clock Selection
WDCS20 Selected Clock
Address: FFFFF6D1H
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
12
13
14
15
16
17
18
19
18
19
20
21
22
23
24
25
9
10
11
12
13
14
15
16
/f
/f
/f
/f
/f
/f
/f
/f
/f
/f
/f
/f
/f
/f
/f
/f
/f
/f
/f
/f
/f
/f
/f
/f
XT
CHAPTER 11 FUNCTIONS OF WATCHDOG TIMER 2
R
R
R
R
R
R
R
R
XX
XX
XX
XX
XX
XX
XX
XX
XT
XT
XT
XT
XT
XT
XT
41.0 ms
81.9 ms
163.8 ms
327.7 ms
655.4 ms
1,310.7 ms
2,621.4 ms
5,242.9 ms
f
8.2 ms
16.4 ms
32.8 ms
65.5 ms
131.1 ms
262.1 ms
524.3 ms
1,048.6 ms
f
15.625 ms
31.25 ms
62.5 ms
125 ms
250 ms
500 ms
1,000 ms
2,000 ms
100 kHz (MIN.)
XX
XT
= 32 MHz
= 32.768 kHz
18.6 ms
37.2 ms
74.5 ms
148.9 ms
297.9 ms
595.8 ms
1,191.6 ms
2,383.1 ms
f
13.1 ms
26.2 ms
52.4 ms
104.9 ms
209.7 ms
419.4 ms
838.9 ms
1,677.7 ms
220 kHz (TYP.)
XX
= 20 MHz
10.2 ms
20.5 ms
41.0 ms
81.9 ms
163.8 ms
327.7 ms
655.4 ms
1,310.7 ms
f
26.2 ms
52.4 ms
104.9 ms
209.7 ms
419.4 ms
838.9 ms
1,677.7 ms
3,355.4 ms
400 kHz (MAX.)
XX
= 10 MHz
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