UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 195

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
Note The CLS bit is a read-only bit.
Cautions 1. Do not change the CPU clock (by using the CK3 to CK0 bits) while CLKOUT is being
Remark ×: don’t care
2. Use a bit manipulation instruction to manipulate the CK3 bit.
After reset: 03H
PCC
output.
manipulation instruction, do not change the set values of the CK2 to CK0 bits.
•
•
•
CLS
MFRC
Even if the MCK bit is set (1) while the system is operating with the main clock as
the CPU clock, the operation of the main clock does not stop. It stops after the
CPU clock has been changed to the subclock.
Before setting the MCK bit from 0 to 1, stop the on-chip peripheral functions
operating with the main clock.
When the main clock is stopped and the device is operating with the subclock,
clear (0) the MCK bit and secure the oscillation stabilization time by software
before switching the CPU clock to the main clock or operating the on-chip
peripheral functions.
MCK
FRC
CK3
FRC
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
1
Note
Used
Not used
Oscillation enabled
Oscillation stopped
Used
Not used
Main clock operation
Subclock operation
R/W
MCK
CK2
< >
0
0
0
0
1
1
1
×
Address: FFFFF828H
MFRC
CK1
0
0
1
1
0
0
1
×
Use of main clock on-chip feedback resistor
Use of subclock on-chip feedback resistor
CLS
Main clock oscillator control
CK0
< >
Status of CPU clock (f
0
1
0
1
0
1
×
×
Note
f
f
f
f
f
f
Setting prohibited
f
CHAPTER 6 CLOCK GENERATION FUNCTION
XX
XX
XX
XX
XX
XX
XT
CK3
< >
/2
/4
/8
/16
/32
Clock selection (f
CK2
CPU
)
CK1
CLK
/f
CPU
When using an 8-bit
)
CK0
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