UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 869

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
Asynchro-
nous serial
interface A
(UARTA)
3-wire
variable-
length
serial I/O
(CSIB)
Function
Start up
UARTAn
Stop UARTAn
Transmit mode
Continuous
transmission
CSIB4 and
UARTA0 mode
switching
CSIB0 and
I
switching
CBnCTL0
register
CBnCTL1
register
CBnCTL2
register
Continuous
transfer mode
(master mode,
transmission
mode)
Continuous
transfer mode
(slave mode,
transmission
mode)
Clock timing
PRSM1 to
PRSM3 registers
PRSCM1 to
PRSCM3
registers
2
C01 mode
Details of
Function
Start up the UARTAn in the following sequence.
<1> Set the UAnCTL0.UAnPWR bit to 1.
<2> Set the ports.
<3> Set the UAnCTL0.UAnTXE bit to 1, UAnCTL0.UAnRXE bit to 1.
Stop the UARTAn in the following sequence.
<1> Set the UAnCTL0.UAnTXE bit to 0, UAnCTL0.UAnRXE bit to 0.
<2> Set the ports and set the UAnCTL0.UAnPWR bit to 0 (it is not a problem if
In transmit mode (UAnCTL0.UAnPWR bit = 1 and UAnCTL0.UAnTXE bit = 1), do
not overwrite the same value to the UAnTX register by software because
transmission starts by writing to this register. To transmit the same value
continuously, overwrite the same value.
In continuous transmission, the communication rate from the stop bit to the next
start bit is extended 2 base clocks more than usual. However, the reception side
initializes the timing by detecting the start bit, so the reception result is not
affected.
The transmit/receive operation of CSIB4 and UARTA0 is not guaranteed if these
functions are switched during transmission or reception. Be sure to disable the
one that is not used.
The transmit/receive operation of CSIB0 and I
functions are switched during transmission or reception. Be sure to disable the
one that is not used.
To forcibly suspend transmission/reception, clear the CBnPWR bit to 0 instead of
the CBnRXE and CBnTXE bits. At this time, the clock output is stopped.
Be sure to clear bits 3 and 2 to “0”.
The CBnCTL1 register can be rewritten only when the CBnCTL0.CBnPWR bit =
0.
Set the communication clock (f
The CBnCTL2 register can be rewritten only when the CBnCTL0.CBnPWR bit = 0
or when both the CBnTXE and CBnRXE bits = 0.
In continuous transmission mode, the reception completion interrupt request
signal (INTCBnR) is not generated.
In continuous transmission mode, the reception completion interrupt request
signal (INTCBnR) is not generated.
In single transfer mode, writing to the CBnTX register with the CBnTSF bit set to 1
is ignored. This has no influence on the operation during transfer.
For example, if the next data is written to the CBnTX register when DMA is started
by generating the INTCBnR signal, the written data is not transferred because the
CBnTSF bit is set to 1.
Use the continuous transfer mode, not the single transfer mode, for such
applications.
Do not rewrite the PRSMm register during operation.
Set the PRSMm register before setting the BGCEm bit to 1.
Do not rewrite the PRSCMm register during operation.
Set the PRSCMm register before setting the PRSMm.BGCEm bit to 1.
port setting is not changed).
CCLK
) to 8 MHz or lower.
Cautions
2
C01 is not guaranteed if these
APPENDIX E LIST OF CAUTIONS
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