UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 870

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
3-wire
variable-
length
serial I/O
(CSIB)
I
2
Function
C bus
Baud rage
generation
When
transferring
transmit data
and receive
data using DMA
transfer
CBnCTL0
register
CBnCTL1
register
CBnCTL2
register
Communication
types 2, 4
I
UARTA2 and
I
switching
CSIB0 and
I
switching
UARTA1 and
I
switching
IICC0 to IICC2
registers
2
2
2
2
C bus
C00 mode
C01 mode
C02 mode
Details of
Function
Set f
When transferring transmit data and receive data using DMA transfer, error
processing cannot be performed even if an overrun error occurs during serial
transfer. Check that the no overrun error has occurred by reading the
CBnSTR.CBnOVE bit after DMA transfer has been completed.
In regards to registers that are forbidden from being rewritten during operations
(CBnCTL0.CBnPWR bit is 1), if rewriting has been carried out by mistake during
operations, set the CBnCTL0.CBnPWR bit to 0 once, then initialize CSIBn.
Registers to which rewriting during operation are prohibited are shown below.
• CBnCTL0 register: CBnTXE, CBnRXE, CBnDIR, CBnTMS bits
• CBnCTL1 register: CBnCKP, CBnDAP, CBnCKS2 to CBnCKS0 bits
• CBnCTL2 register: CBnCL3 to CBnCL0 bits
In communication type 2 and 4 (CBnCTL1.CBnDAP bit = 1), the
CBnSTR.CBnTSF bit is cleared half a SCKBn clock after occurrence of a
reception complete interrupt (INTCBnR).
In the single transfer mode, writing the next transmit data is ignored during
communication (CBnTSF bit = 1), and the next communication is not started. Also
if reception-only communication (CBnCTL0.CBnTXE bit = 0, CBnCTL0.CBnRXE
bit = 1) is set, the next communication is not started even if the receive data is
read during communication (CBnTSF bit = 1).
Therefore, when using the single transfer mode with communication type 2 or 4
(CBnDAP bit = 1), pay particular attention to the following.
• To start the next transmission, confirm that CBnTSF bit = 0 and then write the
• To perform the next reception continuously when reception-only communication
Or, use the continuous transfer mode instead of the single transfer mode. Use of
the continuous transfer mode is recommend especially for using DMA.
P41/SCL01, P90/SDA02, and P91/SCL02 pins as the serial transmit/receive data
I/O pins (SDA00 to SDA02) and serial clock I/O pins (SCL00 to SCL02),
respectively, and set them to N-ch open-drain output.
The transmit/receive operation of UARTA2 and I
functions are switched during transmission or reception. Be sure to disable the
one that is not used.
The transmit/receive operation of CSIB0 and I
functions are switched during transmission or reception. Be sure to disable the
one that is not used.
The transmit/receive operation of UARTA1 and I
functions are switched during transmission or reception. Be sure to disable the
one that is not used.
If the I
and the SDA0n line is low level, the start condition is detected immediately. To
avoid this, after enabling the I
with a bit manipulation instruction.
To use the I
transmit data to the CBnTX register.
(CBnTXE bit = 0, CBnRXE bit = 1) is set, confirm that CBnTSF bit = 0 and then
read the CBnRX register.
BRGm
2
Cn operation is enabled (IICEn bit = 1) when the SCL0n line is high level
to 8 MHz or lower.
2
C bus function, use the P38/SDA00, P39/SCL00, P40/SDA01,
2
Cn operation, immediately set the LRELn bit to 1
Cautions
2
C01 is not guaranteed if these
2
2
C00 is not guaranteed if these
C02 is not guaranteed if these
APPENDIX E LIST OF CAUTIONS
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