UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 212

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
(5) TMPn I/O control register 2 (TPnIOC2)
The TPnIOC2 register is an 8-bit register that controls the valid edge of the external event count input signal (TIPn0
pin) and external trigger input signal (TIPn0 pin).
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
(n = 0 to 5)
TPnIOC2
After reset: 00H
Cautions 1. Rewrite the TPnEES1, TPnEES0, TPnETS1, and TPnETS0
TPnEES1
TPnETS1
0
0
1
1
0
0
1
1
7
0
TPnEES0
TPnETS0
R/W
2. The TPnEES1 and TPnEES0 bits are valid only when the
3. The TPnETS1 and TPnETS0 bits are valid only when the
6
0
0
1
0
1
0
1
0
1
bits when the TPnCTL0.TPnCE bit = 0. (The same value
can be written when the TPnCE bit = 1.) If rewriting was
mistakenly performed, clear the TPnCE bit to 0 and then
set the bits again.
TPnCTL1.TPnEEE bit = 1 or when the external event
count mode (TPnCTL1.TPnMD2 to TPnCTL1.TPnMD0 bits
= 001) has been set.
external trigger pulse output mode (TPnCTL1.TPnMD2 to
TPnCTL1.TPnMD0 bits = 010) or the one-shot pulse
output mode (TPnCTL1.TPnMD2 to TPnCTL1.TPnMD0 =
011) is set.
Address:
External event count input signal (TIPn0 pin) valid edge setting
No edge detection (external event count invalid)
Detection of rising edge
Detection of falling edge
Detection of both edges
No edge detection (external trigger invalid)
Detection of rising edge
Detection of falling edge
Detection of both edges
External trigger input signal (TIPn0 pin) valid edge setting
5
0
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP)
TP0IOC2 FFFFF594H, TP1IOC2 FFFFF5A4H,
TP2IOC2 FFFFF5B4H, TP3IOC2 FFFFF5C4H,
TP4IOC2 FFFFF5D4H, TP5IOC2 FFFFF5E4H
4
0
TPnEES1 TPnEES0 TPnETS1 TPnETS0
3
2
1
0
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