UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 78

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
(2) Accessing specific on-chip peripheral I/O registers
16-bit timer/event counter P (TMP)
(n = 0 to 5)
16-bit timer/event counter Q (TMQ)
Watchdog timer 2 (WDT2)
Real-time output function (RTO)
A/D converter
I
CRC
2
C00 to I
This product has two types of internal system buses.
One is a CPU bus and the other is a peripheral bus that interfaces with low-speed peripheral hardware.
The clock of the CPU bus and the clock of the peripheral bus are asynchronous. If an access to the CPU and an
access to the peripheral hardware conflict, therefore, unexpected illegal data may be transferred. If there is a
possibility of a conflict, the number of cycles for accessing the CPU changes when the peripheral hardware is
accessed, so that correct data is transferred. As a result, the CPU does not start processing of the next instruction
but enters the wait state. If this wait state occurs, the number of clocks required to execute an instruction increases
by the number of wait clocks shown below.
This must be taken into consideration if real-time processing is required.
When specific on-chip peripheral I/O registers are accessed, more wait states may be required in addition to the
wait states set by the VSWC register.
The access conditions and how to calculate the number of wait states to be inserted (number of CPU clocks) at this
time are shown below.
Number of clocks necessary for access = 3 + i + j + (2 + j) × k
Caution Accessing the above registers is prohibited in the following statuses. If a wait cycle is generated,
Remark
Peripheral Function
2
C02
it can only be cleared by a reset.
•
•
i: Values (0 or 1) of higher 4 bits of VSWC register
j: Values (0 or 1) of lower 4 bits of VSWC register
When the CPU operates with the subclock and the main clock oscillation is stopped
When the CPU operates with the internal oscillation clock
TPnCNT
TPnCCR0, TPnCCR1
TQ0CNT
TQ0CCR0 to TQ0CCR3
WDTM2
RTBL0, RTBH0
ADA0M0
ADA0CR0 to ADA0CR11
ADA0CR0H to ADA0CR11H
IICS0 to IICS2
CRCD
Register Name
Read
Write
Read
Read
Write
Read
Write
(when WDT2 operating)
Write
(RTPC0.RTPOE0 bit = 0)
Read
Read
Read
Read
Write
Access
CHAPTER 3 CPU FUNCTION
1 or 2
• 1st access: No wait
• Continuous write: 3 or 4
1 or 2
1 or 2
• 1st access: No wait
• Continuous write: 3 or 4
1 or 2
3
1
1 or 2
1 or 2
1 or 2
1
1
k
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