UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 412

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
11.3 Registers
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
(1) Watchdog timer mode register 2 (WDTM2)
Cautions 1. For details of the WDCS20 to WDCS24 bits, see Table 11-2 Watchdog Timer 2 Clock
Caution Accessing the WDTM2 register is prohibited in the following statuses. For details, see 3.4.8 (2)
The WDTM2 register sets the overflow time and operation clock of watchdog timer 2.
This register can be read or written in 8-bit units. This register can be read any number of times, but it can be
written only once following reset release.
Reset sets this register to 67H.
2. Although watchdog timer 2 can be stopped just by stopping the operation of the internal
3. If the WDTM2 register is rewritten twice after reset, an overflow signal is forcibly
4. To intentionally generate an overflow signal, write data to the WDTM2 register only twice,
5. To stop the operation of watchdog timer 2, set the RCM.RSTOP bit to 1 (to stop the
WDTM2
Selection.
oscillator, clear the WDTM2 register to 00H to securely stop the timer (to avoid selection
of the main clock or subclock due to an erroneous write operation).
generated and the counter is reset.
or write a value other than “ACH” to the WDTE register only once.
However, when watchdog timer 2 is set to stop operation, an overflow signal is not
generated even if data is written to the WDTM2 register only twice, or a value other than
“ACH” is written to the WDTE register only once.
internal oscillator) and write 00H in the WDTM2 register. If the RCM.RSTOP bit cannot be
set to 1, set the WDCS23 bit to 1 (2
IDLE1, IDLW2, sub-IDLE, and subclock operation modes).
Accessing specific on-chip peripheral I/O registers.
•
•
After reset: 67H
When the CPU operates with the subclock and the main clock oscillation is stopped
When the CPU operates with the internal oscillation clock
WDM21
0
0
1
0
WDM20
WDM21
R/W
0
1
–
Address: FFFFF6D0H
Stops operation
Non-maskable interrupt request mode
(generation of INTWDT2 signal)
Reset mode (generation of WDT2RES signal)
WDM20 WDCS24 WDCS23 WDCS22 WDCS21 WDCS20
Selection of operation mode of watchdog timer 2
CHAPTER 11 FUNCTIONS OF WATCHDOG TIMER 2
n
/f
XX
is selected and the clock can be stopped in the
Page 396 of 870