UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 453

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
(10) High-speed conversion mode
(11) A/D conversion time
(12) Variation of A/D conversion results
(13) A/D conversion result hysteresis characteristics
In the high-speed conversion mode, rewriting of the ADA0M0, ADA0M2, ADA0S, ADA0PFM, and ADA0PFT
registers and trigger input during the stabilization time are prohibited.
A/D conversion time is the total time of stabilization time, conversion time, wait time, and trigger response time
(for details of these times, refer to Table 13-2 Conversion Time Selection in Normal Conversion Mode
(ADA0HS1 Bit = 0) and Table 13-3 Conversion Time Selection in High-Speed Conversion Mode (ADA0HS1
Bit = 1)).
During A/D conversion in the normal conversion mode, if the ADA0M0, ADA0M2, ADA0S, ADA0PFM, and
ADA0PFT registers are written or a trigger is input, reconversion is carried out. However, if the stabilization time
end timing conflicts with the writing to these registers, or if the stabilization time end timing conflicts with the
trigger input, the stabilization time of 64 clocks is reinserted.
If a conflict occurs again with the reinserted stabilization time end timing, the stabilization time is reinserted.
Therefore do not set the trigger input interval and control register write interval to 64 clocks or below.
The results of the A/D conversion may vary depending on the fluctuation of the supply voltage, or may be affected
by noise. To reduce the variation, take counteractive measures with the program such as averaging the A/D
conversion results.
The successive comparison type A/D converter holds the analog input voltage in the internal sample & hold
capacitor and then performs A/D conversion. After the A/D conversion has finished, the analog input voltage
remains in the internal sample & hold capacitor. As a result, the following phenomena may occur.
• When the same channel is used for A/D conversions, if the voltage is higher or lower than the previous A/D
• When switching the analog input channel, hysteresis characteristics may appear where the conversion result is
conversion, then hysteresis characteristics may appear where the conversion result is affected by the previous
value. Thus, even if the conversion is performed at the same potential, the result may vary.
affected by the previous channel value. This is because one A/D converter is used for the A/D conversions.
Thus, even if the conversion is performed at the same potential, the result may vary.
CHAPTER 13 A/D CONVERTER
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