UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 74

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
(1) Setting data to special registers
Set data to the special registers in the following sequence.
<1>
<2>
<3>
<4>
(<5> to <9> Insert NOP instructions (5 instructions).)
<10>
There is no special sequence to read a special register.
Note Five NOP instructions or more must be inserted immediately after setting the IDLE1 mode, IDLE2 mode, or
Cautions 1. When a store instruction is executed to store data in the command register, interrupts are not
[Example] With PSC register (setting standby mode)
<1>CLR1 0, DCHCn[r0]
<2>MOV0x02, r10
<3>ST.B r10, PRCMD[r0] ; Write PRCMD register.
<4>ST.B r10, PSC[r0]
<5>NOP
<6>NOP
<7>NOP
<8>NOP
<9>NOP
<10>SET1 0, DCHCn[r0]
(next instruction)
ST.B r11, PSMR[r0]
STOP mode (by setting the PSC.STP bit to 1).
Note
Note
Note
Note
Note
2. Although dummy data is written to the PRCMD register, use the same general-purpose
Disable DMA operation.
Prepare data to be set to the special register in a general-purpose register.
Write the data prepared in <2> to the PRCMD register.
Write the setting data to the special register (by using the following instructions).
• Store instruction (ST/SST instruction)
• Bit manipulation instruction (SET1/CLR1/NOT1 instruction)
Enable DMA operation if necessary.
acknowledged. This is because it is assumed that steps <3> and <4> above are performed by
successive store instructions. If another instruction is placed between <3> and <4>, and if an
interrupt is acknowledged by that instruction, the above sequence may not be established,
causing malfunction.
register used to set the special register (<4> in Example) to write data to the PRCMD register
(<3> in Example). The same applies when a general-purpose register is used for addressing.
; Set PSMR register (setting IDLE1, IDLE2, and STOP modes).
; Disable DMA operation. n = 0 to 3
; Set PSC register.
; Dummy instruction
; Dummy instruction
; Dummy instruction
; Dummy instruction
; Dummy instruction
; Enable DMA operation. n = 0 to 3
Note
CHAPTER 3 CPU FUNCTION
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