UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 76

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
(3) System status register (SYS)
Status flags that indicate the operation status of the overall system are allocated to this register.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
The PRERR flag operates under the following conditions.
(a) Set condition (PRERR flag = 1)
(b) Clear condition (PRERR flag = 0)
(i) When data is written to a special register without writing anything to the PRCMD register (when <4> is
(ii) When data is written to an on-chip peripheral I/O register other than a special register (including execution
Remark
(i) When 0 is written to the PRERR flag
(ii) When the system is reset
Cautions 1. If 0 is written to the PRERR bit of the SYS register, which is not a special register,
executed without executing <3> in 3.4.7 (1) Setting data to special registers)
of a bit manipulation instruction) after writing data to the PRCMD register (if <4> in 3.4.7 (1) Setting data
to special registers is not the setting of a special register)
After reset:
SYS
2. If data is written to the PRCMD register, which is not a special register, immediately after a
Even if an on-chip peripheral I/O register is read (except by a bit manipulation instruction) between
an operation to write the PRCMD register and an operation to write a special register, the PRERR
flag is not set, and the set data can be written to the special register.
immediately after a write access to the PRCMD register, the PRERR bit is cleared to 0 (the
write access takes precedence).
write access to the PRCMD register, the PRERR bit is set to 1.
PRERR
00H
0
1
0
Protection error did not occur
Protection error occurred
R/W
0
Address:
0
FFFFF802H
Detects protection error
0
0
0
CHAPTER 3 CPU FUNCTION
0
PRERR
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