UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 855

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
Bus
control
functions
Clock
generation
function
Function
Pin status when
internal ROM
EXIMC register
BSC register
DWC0 register
AWC register
BCC register
PCC register
Details of
Function
When a write access is performed to the internal ROM area, address, data, and
control signals are activated in the same way as access to the external memory
area.
Set the EXIMC register from the internal ROM or internal RAM area before
making an external access.
After setting the EXIMC register, be sure to insert a NOP instruction.
Write to the BSC register after reset, and then do not change the set values. Also,
do not access an external memory area until the initial settings of the BSC
register are complete.
Be sure to set bits 14, 12, 10, and 8 to “1”, and clear bits 15, 13, 11, 9, 7, 5, 3,
and 1 to “0”.
The internal ROM and internal RAM areas are not subject to programmable wait,
and are always accessed without a wait state. The on-chip peripheral I/O area is
also not subject to programmable wait, and only wait control from each peripheral
function is performed.
Write to the DWC0 register after reset, and then do not change the set values.
Also, do not access an external memory area until the initial settings of the DWC0
register are complete.
When the V850ES/JG3 is used in separate bus mode and operated at f
MHz, be sure to insert one or more waits.
Be sure to clear bits 15, 11, 7, and 3 to “0”.
Address setup wait and address hold wait cycles are not inserted when the
internal ROM area, internal RAM area, and on-chip peripheral I/O areas are
accessed.
Write to the AWC register after reset, and then do not change the set values.
Also, do not access an external memory area until the initial settings of the AWC
register are complete.
When the V850ES/JG3 is operated at f
hold wait and the address setup wait.
Be sure to set bits 15 to 8 to “1”.
The internal ROM, internal RAM, and on-chip peripheral I/O areas are not subject
to idle state insertion.
Write to the BCC register after reset, and then do not change the set values. Also,
do not access an external memory area until the initial settings of the BCC
register are complete.
Be sure to set bits 15, 13, 11, and 9 to “1”, and clear bits 14, 12, 10, 8, 6, 4, 2,
and 0 to “0”.
Do not change the CPU clock (by using the CK3 to CK0 bits) while CLKOUT is
being output.
Use a bit manipulation instruction to manipulate the CK3 bit. When using an 8-bit
manipulation instruction, do not change the set values of the CK2 to CK0 bits.
When stopping the main clock, stop the PLL. Also stop the operations of the on-
chip peripheral functions operating with the main clock.
If the following conditions are not satisfied, change the CK2 to CK0 bits so that
the conditions are satisfied, then change to the subclock operation mode.
Internal system clock (f
Enable operation of the on-chip peripheral functions operating with the main clock
only after the oscillation of the main clock stabilizes. If their operations are
enabled before the lapse of the oscillation stabilization time, a malfunction may
occur.
CLK
) > Subclock (f
Cautions
XX
XT
> 20 MHz, be sure to insert the address
: 32.768 kHz) × 4
APPENDIX E LIST OF CAUTIONS
XX
> 20
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