UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 471

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
(2) UARTAn control register 1 (UAnCTL1)
(3) UARTAn control register 2 (UAnCTL2)
(4) UARTAn option control register 0 (UAnOPT0)
Caution Do not set the UAnSRT and UAnSTT bits (to 1) during SBF reception (UAnSRF bit = 1).
For details, see 15.7 (2) UARTAn control register 1 (UAnCTL1).
For details, see 15.7 (3) UARTAn control register 2 (UAnCTL2).
The UAnOPT0 register is an 8-bit register that controls the serial transfer operation of the UARTAn register.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 14H.
(n = 0 to 2)
UAnOPT0
After reset: 14H
• SBF (Sync Break Field) reception is judged during LIN communication.
• The UAnSRF bit is held at 1 when an SBF reception error occurs, and then SBF
• UAnSRF bit is a read-only bit.
• This is the SBF reception trigger bit during LIN communication, and when read,
• Set the UAnSRT bit after setting the UAnPWR bit = UAnRXE bit = 1.
• This is the SBF transmission trigger bit during LIN communication, and when read,
• Set the UAnSTT bit after setting the UAnPWR bit = UAnTXE bit = 1.
UAnSRF
UAnSRT
UAnSTT
UAnSRF
reception is started again.
“0” is always read. For SBF reception, set the UAnSRT bit (to 1) to enable SBF
reception.
“0” is always read.
<7>
0
1
0
1
0
1
When the UAnCTL0.UAnPWR bit = UAnCTL0.UAnRXE bit = 0 are set.
Also upon normal end of SBF reception.
During SBF reception
SBF reception trigger
SBF transmission trigger
UAnSRT UAnSTT UAnSLS2 UAnSLS1 UAnSLS0 UAnTDL UAnRDL
R/W
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA)
6
Address: UA0OPT0 FFFFFA03H, UA1OPT0 FFFFFA13H,
5
UA2OPT0 FFFFFA23H
SBF transmission trigger
4
SBF reception trigger
SBF reception flag
−
−
3
2
1
0
Page 455 of 870
(1/2)