UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 673

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
19.4 Software Exception
19.4.1 Operation
00000040H, and if the vector is 10H to 1FH, it becomes 00000050H.
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
A software exception is generated when the CPU executes the TRAP instruction, and can always be acknowledged.
If a software exception occurs, the CPU performs the following processing, and transfers control to the handler routine.
<1> Saves the restored PC to EIPC.
<2> Saves the current PSW to EIPSW.
<3> Writes an exception code to the lower 16 bits (EICC) of ECR (interrupt source).
<4> Sets the PSW.EP and PSW.ID bits to 1.
<5> Sets the handler address (00000040H or 00000050H) corresponding to the software exception to the PC, and
The processing of a software exception is shown below.
The handler address is determined by the TRAP instruction’s operand (vector). If the vector is 00H to 0FH, it becomes
Note TRAP instruction format: TRAP vector (the vector is a value from 00H to 1FH.)
transfers control.
CPU processing
Figure 19-9. Software Exception Processing
CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION
EIPC
EIPSW
ECR.EICC
PSW.EP
PSW.ID
PC
Exception processing
TRAP instruction
Restored PC
PSW
Exception code
1
1
Handler address
Note
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