UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 452

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
(7) AV
(8) Reading ADA0CRn register
(9) Standby mode
(a) The AV
(b) The AV
(c) If the source supplying power to the AV
When the ADA0M0 to ADA0M2, ADA0S, ADA0PFM, or ADA0PFT register is written, the contents of the ADA0CRn
register may be undefined. Read the conversion result after completion of conversion and before writing to the
ADA0M0 to ADA0M2, ADA0S, ADA0PFM, or ADA0PFT register.
acknowledged, the contents of the ADA0CRn register may be undefined.
completion of conversion and before the next external/timer trigger is acknowledged. The correct conversion result
may not be read at a timing different from the above.
Because the A/D converter stops operating in the STOP mode, conversion results are invalid, so power
consumption can be reduced. Operations are resumed after the STOP mode is released, but the A/D conversion
results after the STOP mode is released are invalid. When using the A/D converter after the STOP mode is
released, before setting the STOP mode or releasing the STOP mode, clear the ADA0M0.ADA0CE bit to 0 then set
the ADA0CE bit to 1 after releasing the STOP mode.
In the IDLE1, IDLE2, or subclock operation mode, operation continues. To lower the power consumption, therefore,
clear the ADA0M0.ADA0CE bit to 0. In the IDLE1 and IDLE2 modes, since the analog input voltage value cannot
be retained, the A/D conversion results after the IDLE1 and IDLE2 modes are released are invalid. The results of
conversions before the IDLE1 and IDLE2 modes were set are valid.
Note Parasitic inductance
REF0
function ports. In an application where a backup power supply is used, be sure to supply the same voltage as
V
the AV
voltage may fluctuate due to the current that flows during conversion (especially, immediately after the
conversion operation enable bit ADA0CE has been set to 1). As a result, the conversion accuracy may drop.
To avoid this, it is recommended to connect a capacitor across the AV
reference voltage fluctuation as shown in Figure 13-15.
a diode), the voltage when conversion is enabled may be lower than the voltage when conversion is stopped,
because of a voltage drop caused by the A/D conversion current.
DD
pin
to the AV
REF0
REF0
REF0
pin has a high impedance or if the power supply has a low current supply capability, the reference
pin is also used as the reference voltage pin of the A/D converter. If the source supplying power to
pin is used as the power supply pin of the A/D converter and also supplies power to the alternate-
REF0
pin as shown in Figure 13-15.
Main power supply
Figure 13-15. AV
REF0
Note
REF0
pin has a high DC resistance (for example, because of insertion of
Pin Processing Example
AV
AV
REF0
SS
Also, when an external/timer trigger is
CHAPTER 13 A/D CONVERTER
REF0
Read the conversion result after
and AV
SS
pins to suppress the
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