UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 849

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
Notes 12. In this instruction, for convenience of mnemonic description, the source register is made reg2, but the reg1
13. i i i i i : Lower 5 bits of imm9.
14. Do not specify the same register for general-purpose registers reg1 and reg3.
15. sp/imm: specified by bits 19 and 20 of the sub-opcode.
16. ff = 00: Load sp in ep.
17. If imm = imm32, n + 3 clocks.
18. r r r r r : Other than 00000.
19. ddddddd: Higher 7 bits of disp8.
20. dddd: Higher 4 bits of disp5.
21. dddddd: Higher 6 bits of disp8.
field is used in the opcode. Therefore, the meaning of register specification in the mnemonic description
and in the opcode differs from other instructions.
r r r r r
RRRRR = reg2 specification
I I I I : Higher 4 bits of imm9.
01: Load sign expanded 16-bit immediate data (bits 47 to 32) in ep.
10: Load 16-bit logically left shifted 16-bit immediate data (bits 47 to 32) in ep.
11: Load 32-bit immediate data (bits 63 to 32) in ep.
= regID specification
APPENDIX D INSTRUCTION SET LIST
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