UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 574

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
17.6 I
The transfer timing for the “start condition”, “address”, “transfer direction specification”, “data”, and “stop condition”
generated on the I
data).
low-level period can be extended and a wait state can be inserted (n = 0 to 2).
17.6.1 Start condition
start condition for the SCL0n and SDA0n pins is a signal that the master device outputs to the slave device when starting a
serial transfer. The slave device can defect the start condition (n = 0 to 2).
1). When a start condition is detected, the IICSn.STDn bit is set (1) (n = 0 to 2).
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
The following section describes the I
The master device generates the start condition, slave address, and stop condition.
ACK can be generated by either the master or slave device (normally, it is generated by the device that receives 8-bit
The serial clock (SCL0n) is continuously output by the master device. However, in the slave device, the SCL0n pin’s
A start condition is met when the SCL0n pin is high level and the SDA0n pin changes from high level to low level. The
A start condition is output when the IICCn.STTn bit is set (1) after a stop condition has been detected (IICSn.SPDn bit =
Caution When the IICCn.IICEn bit of the V850ES/JG3 is set to 1 while communications with other devices are
2
C Bus Definitions and Control Methods
in progress, the start condition may be detected depending on the status of the communication line.
Be sure to set the IICCn.IICEn bit to 1 when the SCL0n and SDA0n lines are high level.
SDA0n
SCL0n
2
C bus’s serial data bus is shown below.
Start
condition
Address
1 to 7
Figure 17-7. I
SDA0n
SCL0n
2
R/W
C bus’s serial data communication format and the signals used by the I
8
H
Figure 17-8. Start Condition
ACK
9
2
C Bus Serial Data Transfer Timing
1 to 8
Data
ACK
9
1 to 8
Data
ACK
9
Stop
condition
CHAPTER 17 I
Page 558 of 870
2
C BUS
2
C bus.