UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 277

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
(c) Processing of overflow when two capture registers are used
Care must be exercised in processing the overflow flag when two capture registers are used. First, an example
of incorrect processing is shown below.
The following problem may occur when two pulse widths are measured in the free-running timer mode.
<1> Read the TPnCCR0 register (setting of the default value of the TIPn0 pin input).
<2> Read the TPnCCR1 register (setting of the default value of the TIPn1 pin input).
<3> Read the TPnCCR0 register.
<4> Read the TPnCCR1 register.
When two capture registers are used, and if the overflow flag is cleared to 0 by one capture register, the other
capture register may not obtain the correct pulse width.
Use software when using two capture registers. An example of how to use software is shown below.
TPnCCR0 register
TPnCCR1 register
Read the overflow flag. If the overflow flag is 1, clear it to 0.
Because the overflow flag is 1, the pulse width can be calculated by (10000H + D
Read the overflow flag. Because the flag is cleared in <3>, 0 is read.
Because the overflow flag is 0, the pulse width can be calculated by (D
INTTPnOV signal
TIPn0 pin input
TIPn1 pin input
16-bit counter
TPnOVF bit
Example of incorrect processing when two capture registers are used
TPnCE bit
FFFFH
0000H
D
00
<1>
D
10
CHAPTRER 7 16-BIT TIMER/EVENT COUNTER P (TMP)
<2>
D
00
D
D
01
10
<3>
D
11
<4>
11
D
− D
01
10
) (incorrect).
D
11
01
− D
00
).
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