UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 272

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
Figure 7-32. Software Processing Flow in Free-Running Timer Mode (Compare Function) (2/2)
Remark
n = 0 to 5
<1> Count operation start flow
<2> Overflow flag clear flow
<3> Count operation stop flow
(TPnCKS0 to TPnCKS2 bits)
TPnOVF bit (CLR TPnOVF).
Execute instruction to clear
Read TPnOPT0 register
Register initial setting
(check overflow flag).
TPnCCR0 register,
TPnOPT0 register,
TPnCTL1 register,
TPnIOC0 register,
TPnIOC2 register,
TPnCCR1 register
TPnCTL0 register
TPnOVF bit = 1
TPnCE bit = 1
TPnCE bit = 0
START
STOP
YES
CHAPTRER 7 16-BIT TIMER/EVENT COUNTER P (TMP)
NO
Counter is initialized and
counting is stopped by
clearing TPnCE bit to 0.
Initial setting of these registers
is performed before setting the
TPnCE bit to 1.
The TPnCKS0 to TPnCKS2 bits
can be set at the same time
when counting has been started
(TPnCE bit = 1).
Page 256 of 870