UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 81

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
4.3
Note The value written to the output latch is retained until a new value is written to the output latch.
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
Control register
Ports
Setting of PMn Register
(1) Port n register (Pn)
Port Configuration
Data is input from or output to an external device by writing or reading the Pn register.
The Pn register consists of a port latch that holds output data, and a circuit that reads the status of pins.
Each bit of the Pn register corresponds to one pin of port n, and can be read or written in 1-bit units.
Data is written to or read from the Pn register as follows, regardless of the setting of the PMCn register.
Output mode
(PMnm = 0)
(PMnm = 1)
Input mode
Item
Pn
After reset: 00H (output latch)
Pnm
Pn7
0
1
7
Port n mode register (PMn: n = 0, 1, 3 to 5, 7, 9, CD, CM, CT, DH, DL)
Port n mode control register (PMCn: n = 0, 3 to 5, 9, CM, CT, DH, DL)
Port n function control register (PFCn: n = 0, 3 to 5, 9)
Port n function control expansion register (PFCEn: n = 3, 5, 9)
Port n function register (PFn: n = 0, 3 to 5, 9)
I/O: 84
Data is written to the output latch
In the port mode (PMCn = 0), the contents of the output
latch are output from the pins.
Data is written to the output latch.
The pin status is not affected
Outputs 0.
Outputs 1.
Pn6
6
Table 4-3. Writing/Reading Pn Register
Writing to Pn Register
Pn5
Table 4-2. Port Configuration
5
Control of output data (in output mode)
R/W
Note
Pn4
.
7
Note
.
Pn3
3
Configuration
Pn2
2
The value of the output latch is read.
The pin status is read.
CHAPTER 4 PORT FUNCTIONS
Pn1
1
Reading from Pn Register
Pn0
0
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