UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 381

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
(d) Processing of overflow if capture trigger interval is long
If the pulse width is greater than one cycle of the 16-bit counter, care must be exercised because an overflow
may occur more than once from the first capture trigger to the next. First, an example of incorrect processing is
shown below.
The following problem may occur when a long pulse width in the free-running timer mode.
<1> Read the TQ0CCRm register (setting of the default value of the TIQ0m pin input).
<2> An overflow occurs. Nothing is done by software.
<3> An overflow occurs a second time. Nothing is done by software.
<4> Read the TQ0CCRm register.
If an overflow occurs twice or more when the capture trigger interval is long, the correct pulse width may not be
obtained.
If the capture trigger interval is long, slow the count clock to lengthen one cycle of the 16-bit counter, or use
software. An example of how to use software is shown next.
TQ0CCRm register
Read the overflow flag. If the overflow flag is 1, clear it to 0.
Because the overflow flag is 1, the pulse width can be calculated by (10000H + D
(incorrect).
Actually, the pulse width must be (20000H + D
INTTQ0OV signal
TIQ0m pin input
16-bit counter
TQ0OVF bit
Example of incorrect processing when capture trigger interval is long
TQ0CE bit
FFFFH
0000H
CHAPTRER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
D
m0
<1> <2>
m1
− D
m0
1 cycle of 16-bit counter
) because an overflow occurs twice.
Pulse width
D
m0
<3> <4>
D
m1
D
m1
Page 365 of 870
m1
− D
m0
)