UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 641

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
18.10 DMA Abort Factors
chip peripheral I/O.
18.11 End of DMA Transfer
cleared to 0 and TCn bit is set to 1, a DMA transfer end interrupt request signal (INTDMAn) is generated for the interrupt
controller (INTC) (n = 0 to 3).
transfer by using the DMA transfer end interrupt or polling the TCn bit.
18.12 Operation Timing
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
DMA transfer is aborted if a bus hold occurs.
The same applies if transfer is executed between the internal memory/on-chip peripheral I/O and internal memory/on-
When the bus hold is cleared, DMA transfer is resumed.
When DMA transfer has been completed the number of times set to the DBCn register and when the DCHCn.Enn bit is
The V850ES/JG3 does not output a terminal count signal to an external device. Therefore, confirm completion of DMA
Figures 18-1 to 18-4 show DMA operation timing.
CHAPTER 18 DMA FUNCTION (DMA CONTROLLER)
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