UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 611

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
17.14.2 When communication reservation function is disabled (IICFn.IICRSVn bit = 1)
rejected and a start condition is not generated. There are two modes in which the bus is not used.
shown in Table 17-7 is required until the STCFn flag is set after setting the STTn bit to 1. Therefore, secure the time by
software.
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
When the IICCn.STTn bit is set when the bus is not used in a communication during bus communication, this request is
• When arbitration results in neither master nor slave operation
• When an extension code is received and slave operation is disabled (ACK is not returned and the bus was released
To confirm whether the start condition was generated or request was rejected, check the IICFn.STCFn flag. The time
when the IICCn.LRELn bit was set to 1) (n = 0 to 2).
Remarks 1. ×: don’t care
OCKSENm
1
1
1
1
0
2. n = 0 to 2
m = 0, 1
OCKSm1
0
0
1
1
0
OCKSm0
Table 17-7. Wait Periods
0
1
0
1
0
CLn1
1
0
0
0
0
CLn0
×
×
×
×
0
Wait Period
10 clocks
15 clocks
20 clocks
25 clocks
5 clocks
CHAPTER 17 I
Page 595 of 870
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C BUS