UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 429

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
Remark
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
ADA0FR3 to
Others
ADA0FR0
0000
0001
0010
0011
0100
0101
0110
1000
1001
1010
1011
0111
Bits
Stabilization time:
Conversion time:
Trigger response time: If a software trigger, external trigger, or timer trigger is generated after the stabilization
Wait time:
In the normal conversion mode, the conversion is started after the stabilization time elapsed from the
ADA0M0.ADA0CE bit is set to 1, and A/D conversion is performed only during the conversion time (2.6 to 10.4
μ
(INTAD) is generated after the wait time is elapsed.
Because the conversion operation is stopped during the wait time, operation current can be reduced.
Cautions 1. Set as 2.6
66/f
131/f
196/f
259/f
311/f
363/f
415/f
467/f
519/f
571/f
623/f
675/f
Setting prohibited
s). Operation is stopped after the conversion ends and the A/D conversion end interrupt request signal
Stabilization Time + Conversion
XX
Table 13-2. Conversion Time Selection in Normal Conversion Mode (ADA0HS1 Bit = 0)
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
(13/f
(50/f
(26/f
(39/f
(50/f
(50/f
(50/f
(50/f
(50/f
(50/f
(50/f
(50/f
Time + Wait Time
XX
2. During A/D conversion, if the ADA0M0, ADA0M2, ADA0S, ADA0PFM, and ADA0PFT
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
+ 26/f
+ 130/f
+ 52/f
+ 78/f
+ 104/f
+ 156/f
+ 182/f
+ 208/f
+ 234/f
+ 260/f
+ 286/f
+ 312/f
registers are written or trigger is input, reconversion is carried out.
stabilization time end timing conflicts with the writing to these registers, or if the
stabilization time end timing conflicts with the trigger input, the stabilization time of 64
clocks is reinserted.
If a conflict occurs again with the reinserted stabilization time end timing, the stabilization
time is reinserted. Therefore do not set the trigger input interval and control register write
interval to 64 clocks or below.
XX
XX
XX
XX
+ 27/f
XX
XX
XX
XX
XX
XX
XX
XX
+ 53/f
+ 79/f
+ 131/f
+ 105/f
+ 157/f
+ 183/f
+ 209/f
+ 235/f
+ 261/f
+ 287/f
+ 313/f
A/D converter setup time (1
Actual A/D conversion time (2.6 to 10.4
Wait time inserted before the next conversion
time, it is inserted before the conversion time.
XX
μ
XX
XX
s ≤ conversion time ≤ 10.4
)
)
)
XX
XX
XX
XX
XX
XX
XX
XX
XX
)
)
)
)
)
)
)
)
)
8.09
9.72
11.34
12.97
14.59
16.22
17.84
19.47
21.09
Setting prohibited Setting prohibited Setting prohibited
Setting prohibited
Setting prohibited
f
XX
= 32 MHz
μ
μ
μ
s
s
μ
μ
μ
μ
μ
μ
s
s
s
s
s
s
s
A/D Conversion Time
6.55
9.80
12.95
15.55
18.15
20.75
23.35
Setting prohibited Setting prohibited Setting prohibited
Setting prohibited Setting prohibited Setting prohibited
Setting prohibited Setting prohibited Setting prohibited
Setting prohibited Setting prohibited Setting prohibited
f
XX
μ
= 20 MHz
μ
μ
s or longer)
μ
μ
μ
μ
μ
s
s
s
s
s
s
s
μ
s.
μ
8.19
12.25
16.19
19.44
22.69
Setting prohibited Setting prohibited
Setting prohibited Setting prohibited
f
s)
XX
= 16 MHz
μ
s
μ
μ
μ
μ
s
s
s
s
CHAPTER 13 A/D CONVERTER
16.50
Setting prohibited
Setting prohibited
Setting prohibited
Setting prohibited
Setting prohibited
f
XX
= 4 MHz
μ
s
Trigger Response
However, if the
Page 413 of 870
Time
3/f
3/f
3/f
3/f
3/f
3/f
3/f
3/f
3/f
3/f
3/f
3/f
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX