UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 337

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
<1> Count operation start flow
<2> TQ0CCR0 to TQ0CCR3 register
<3> TQ0CCR0 register setting change flow
Setting of TQ0CCR0, TQ0CCR2,
(TQ0CKS0 to TQ0CKS2 bits)
Setting of TQ0CCR0 register
Setting of TQ0CCR1 register
TQ0CCR0 to TQ0CCR3
setting change flow
and TQ0CCR3 registers
Register initial setting
TQ0CTL1 register,
TQ0IOC0 register,
TQ0IOC2 register,
TQ0CCR1 register
TQ0CTL0 register
TQ0CE bit = 1
Remark
registers
START
Figure 8-19. Software Processing Flow in External Trigger Pulse Output Mode (2/2)
m = 0 to 3
Initial setting of these
registers is performed
before setting the
TQ0CE bit to 1.
The TQ0CKS0 to
TQ0CKS2 bits can be
set at the same time
when counting is
enabled (TQ0CE bit = 1).
Trigger wait status
Writing of the TQ0CCR1
register must be performed
after writing the TQ0CCR0,
TQ0CCR2, and TQ0CCR3
registers.
When the counter is cleared
after setting, the value
of the TQ0CCRm register is
transferred to the CCRm buffer
registers.
TQ0CCR1 register writing
of the same value is
necessary only when the
set cycle is changed.
When the counter is
cleared after setting,
the value of the TQ0CCRm
register is transferred to
the CCRm buffer register.
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
<4> TQ0CCR1 to TQ0CCR3 register
<6> TQ0CCR1 register setting change flow
<7> Count operation stop flow
<5> TQ0CCR2, TQ0CCR3 register
Setting of TQ0CCR1 register
Setting of TQ0CCR1 register
Setting of TQ0CCR1 register
Setting of TQ0CCR2,
Setting of TQ0CCR2,
setting change flow
setting change flow
TQ0CCR3 registers
TQ0CCR3 registers
TQ0CE bit = 0
STOP
Writing of the TQ0CCR1
register must be performed
when the set duty factor is only
changed after writing the
TQ0CCR2 and TQ0CCR3
registers.
When the counter is cleared
after setting, the value of the
TQ0CCRm register is transferred
to the CCRm buffer register.
TQ0CCR1 register writing of the
same value is necessary only
when the set duty factor of
TOQ02 and TOQ03 pin
outputs is changed.
When the counter is
cleared after setting,
the value of the TQ0CCRm
register is transferred to
the CCRm buffer register.
Only writing of the TQ0CCR1
register must be performed when
the set duty factor is only changed.
When counter is cleared after
setting, the value of the TQ0CCRm
register is transferred to the CCRm
buffer register.
Counting is stopped.
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