UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 333

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
pin. If the trigger is generated again while the counter is operating, the counter is cleared to 0000H and restarted. (The
output of the TOQ00 pin is inverted. The TOQ0k pin outputs a high-level regardless of the status (high/low) when a trigger
is generated.)
value matches the value of the CCR0 buffer register, and the 16-bit counter is cleared to 0000H. The compare match
interrupt request signal INTTQ0CCk is generated when the count value of the 16-bit counter matches the value of the
CCRk buffer register.
counter matches the value of the CCR0 buffer register and the 16-bit counter is cleared to 0000H.
the trigger.
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
TQ0CTL0
The active level width, cycle, and duty factor of the PWM waveform can be calculated as follows.
The compare match request signal INTTQ0CC0 is generated when the 16-bit counter counts next time after its count
The value set to the TQ0CCRm register is transferred to the CCRm buffer register when the count value of the 16-bit
The valid edge of an external trigger input signal, or setting the software trigger (TQ0CTL1.TQ0EST bit) to 1 is used as
Remark
Active level width = (Set value of TQ0CCRk register) × Count clock cycle
Cycle = (Set value of TQ0CCR0 register + 1) × Count clock cycle
Duty factor = (Set value of TQ0CCRk register)/(Set value of TQ0CCR0 register + 1)
(a) TMQ0 control register 0 (TQ0CTL0)
k = 1 to 3, m = 0 to 3
TQ0CE
Figure 8-18. Register Setting for Operation in External Trigger Pulse Output Mode (1/3)
0/1
0
0
0
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
0
TQ0CKS2 TQ0CKS1 TQ0CKS0
0/1
0/1
0/1
Select count clock
0: Stop counting
1: Enable counting
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