UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 540

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
(2) Operation timing
SIBn pin capture
INTCBnR signal
INTCBnT signal
(1) Write 07H to the CBnCTL1 register, and select communication type 1, communication clock (f
(2) Write 00H to the CBnCTL2 register, and set the transfer data length to 8 bits.
(3) Write E3H to the CBnCTL0 register, and select the transmission/reception mode, MSB first, and continuous
(4) The CBnSTR.CBnTSF bit is set to 1 by writing the transmit data to the CBnTX register, and the device
(5) When a serial clock is input, output the transmit data to the SOBn pin in synchronization with the serial
(6) When transfer of the transmit data from the CBnTX register to the shift register is completed and writing to
(7) To continue transmission, write the transmit data to the CBnTX register again after the INTCBnT signal is
(8) When reception of the transfer data length set with the CBnCTL2 register is completed, the reception
(9) When a serial clock is input continuously, continuous transmission/reception is started.
(10) Read the CBnRX register.
(11) When transfer of the transmit data from the CBnTX register to the shift register is completed and writing to
Remark
CBnTSF bit
SCKBn pin
SOBn pin
SIBn pin
timing
external clock (SCKBn), and slave mode.
transfer mode at the same time as enabling the operation of the communication clock (f
waits for a serial clock input.
clock, and capture the receive data of the SIBn pin.
the CBnTX register is enabled, the transmission enable interrupt request signal (INTCBnT) is generated.
generated.
completion interrupt request signal (INTCBnR) is generated, and reading of the CBnRX register is enabled.
the
transmission/reception with the current transmission/reception, do not write to the CBnTX register.
CBnTX
(1)
(2)
(3)
n = 0 to 4
(4)
(5)
register
Bit 7
Bit 7
Bit 6
Bit 6
(6)
Bit 5
Bit 5
is
(7)
enabled,
Bit 4
Bit 4
Bit 3 Bit 2
Bit 3 Bit 2
CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB)
the
Bit 1
Bit 1
INTCBnT
(8) (9) (10)
Bit 0
Bit 0
Bit 7
Bit 7
Bit 6
Bit 6
signal
Bit 5
Bit 5
(11)
Bit 4
Bit 4
is
Bit 3 Bit 2
Bit 3 Bit 2
generated.
Bit 1
Bit 1
(12)
Bit 0
Bit 0
To
CCLK
(13) (15)
end
).
Page 524 of 870
continuous
CCLK
) =
(1/2)