UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 710

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
22.2 Registers to Check Reset Source
occurred can be checked with the reset source flag register (RESF).
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
The V850ES/JG3 has four kinds of reset sources. After a reset has been released, the source of the reset that
(1) Reset source flag register (RESF)
Note The value of the RESF register is cleared to 00H when a reset is executed via the RESET pin. When a
Caution Only “0” can be written to each bit of this register. If writing “0” conflicts with setting the flag
The RESF register is a special register that can be written only by a combination of specific sequences (see 3.4.7
Special registers).
The RESF register indicates the source from which a reset signal is generated.
This register is read or written in 8-bit or 1-bit units.
RESET pin input clears this register to 00H. The default value differs if the source of reset is other than the RESET
pin signal.
reset is executed by the watchdog timer 2 (WDT2), low-voltage detector (LVI), or clock monitor (CLM),
the reset flags of this register (WDT2RF bit, CLMRF bit, and LVIRF bit) are set. However, other sources
are retained.
(occurrence of reset), setting the flag takes precedence.
RESF
After reset: 00H
WDT2RF
CLMRF
LVIRF
0
1
0
1
0
1
0
Note
Not generated
Generated
Not generated
Generated
Not generated
Generated
R/W
0
Address: FFFFF888H
0
Reset signal from WDT2
Reset signal from CLM
Reset signal from LVI
WDT2RF
0
0
CHAPTER 22 RESET FUNCTIONS
CLMRF
LVIRF
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