UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 575

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
17.6.2 Addresses
master device via the bus lines. Therefore, each slave device connected via the bus lines must have a unique address.
matches the data values stored in the SVAn register. If the address data matches the values of the SVAn register, the
slave device is selected and communicates with the master device until the master device generates a start condition or
stop condition (n = 0 to 2).
specification below, are written together to IIC shift register n (IICn) and then output. Received addresses are written to
the IICn register (n = 0 to 2).
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
The 7 bits of data that follow the start condition are defined as an address.
An address is a 7-bit data segment that is output in order to select one of the slave devices that are connected to the
The slave devices include hardware that detects the start condition and checks whether or not the 7-bit address data
The slave address and the eighth bit, which specifies the transfer direction as described in 17.6.3 Transfer direction
The slave address is assigned to the higher 7 bits of the IICn register.
Note The interrupt request signal (INTIICn) is generated if a local address or extension code is received
Remark
during slave device operation.
n = 0 to 2
INTIICn
SDA0n
SCL0n
AD6
1
AD5
2
Figure 17-9. Address
AD4
3
Address
AD3
4
AD2
5
AD1
6
AD0
7
R/W
8
9
Note
CHAPTER 17 I
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2
C BUS