UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 494

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
(4) Baud rate
The baud rate is obtained by the following equation.
The baud rate error is obtained by the following equation.
When using the internal clock, the equation will be as follows (when using the ASCKA0 pin as clock at
UARTA0, calculate using the above equation).
Remark
When using the internal clock, the equation will be as follows (when using the ASCKA0 pin as clock at
UARTA0, calculate the baud rate error using the above equation).
Cautions 1. The baud rate error during transmission must be within the error tolerance on the
Baud rate =
Baud rate =
f
f
m = Value set using the UAnCTL1.UAnCKS3 to UAnCTL1.UAnCKS0 bits (m = 0 to 10)
k = Value set using the UAnCTL2.UAnBRS7 to UAnCTL2.UAnBRS0 bits (k = 4 to 255)
Error (%) =
Error (%) =
2. The baud rate error during reception must satisfy the range indicated in (5) Allowable
UCLK
XX
: Main clock frequency
receiving side.
baud rate range during reception.
= Frequency of base clock selected by the UAnCTL1.UAnCKS3 to UAnCTL1.UAnCKS0 bits
=
Actual baud rate (baud rate with error)
2
2 × k × Target baud rate
f
2 × k
2
UCLK
Target baud rate (correct baud rate)
m+1
m+1
f
XX
× k
× k × Target baud rate
[bps]
[bps]
f
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA)
UCLK
f
XX
− 1 × 100 [%]
− 1 × 100 [%]
− 1 × 100 [%]
Page 478 of 870