UPD70F3740GC-UEU-AX Renesas Electronics America, UPD70F3740GC-UEU-AX Datasheet - Page 640

• Manufacturer Part Number: UPD70F3740GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3740GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3
18.9 DMA Transfer Start Factors
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
There are two types of DMA transfer start factors, as shown below.
(1) Request by software
(2) Request by on-chip peripheral I/O
If the STGn bit is set to 1 while the DCHCn.TCn bit = 1 and Enn bit = 1 (DMA transfer enabled), DMA transfer is
started.
To request the next DMA transfer cycle immediately after that, confirm, by using the DBCn register, that the
preceding DMA transfer cycle has been completed, and set the STGn bit to 1 again (n = 0 to 3).
If an interrupt request is generated from the on-chip peripheral I/O set by the DTFRn register when the
DCHCn.TCn bit = 0 and Enn bit = 1 (DMA transfer enabled), DMA transfer is started.
Cautions 1. Two start factors (software trigger and hardware trigger) cannot be used for one DMA channel.
TCn bit = 0, Enn bit = 1
STGn bit = 1 … Starts the first DMA transfer.
Confirm that the contents of the DBCn register have been updated.
STGn bit = 1 … Starts the second DMA transfer.
Generation of terminal count … Enn bit = 0, TCn bit = 1, and INTDMAn signal is generated.
2. A new transfer request that is generated after the preceding DMA transfer request was
3. The transfer request interval of the same DMA channel varies depending on the setting of bus
If two start factors are simultaneously generated for one DMA channel, only one of them is
valid. The start factor that is valid cannot be identified.
generated or in the preceding DMA transfer cycle is ignored (cleared).
wait in the DMA transfer cycle, the start status of the other channels, or the external bus hold
request. In particular, as described in Caution 2, a new transfer request that is generated for
the same channel before the DMA transfer cycle or during the DMA transfer cycle is ignored.
Therefore, the transfer request intervals for the same DMA channel must be sufficiently
separated by the system. When the software trigger is used, completion of the DMA transfer
cycle that was generated before can be checked by updating the DBCn register.
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CHAPTER 18 DMA FUNCTION (DMA CONTROLLER)
Page 624 of 870